CY62167G Datasheet, PDF (11/19 Pages) Cypress Semiconductor – 16-Mbit (1M Words × 16 Bit) Static RAM with Error-Correcting Code (ECC)

CY62167G Automotive
Switching Waveforms (continued)
Figure 8. Write Cycle No. 2 (CE Controlled) ^{[25, 26, 27]}
ADDRESS
CE
WE
t_WC
t_SA
t_SCE
t_AW
t_PWE
t_HA
t_BW
BHE/
BLE
OE
DATA I/O
t_HZOE
t_SD
t_HD
DATA_IN VALID
Notes
25.
For
CE
all dual chip
is HIGH.
enable
devices,
CE
is
the
logical
combination
of
CE₁
and
CE₂.
When
CE₁
is
LOW
and
CE₂
is
HIGH,
CE
is
LOW;
when
CE₁
is
HIGH
or
CE₂
is
LOW,
26.
The internal write
a write and any of
time of the memory is defined
these signals can terminate a
by the overlap
write by going
IoNf AWCET=IVVE^I.^L,TCheE1da=taV^Ii^Ln,pBuHt sEeoturpBaLnEdohroblodtthim=inVg^ILm, ^aunsdt
rCeEfe²r
=toVt_IhHe.
All signals must be ACTIVE to initiate
edge of the signal that terminates the
write.
27. Data I/O is in high impedance state if CE = V_IH, or OE = V_IH or BHE, and/or BLE = V_IH.
Document Number: 001-84902 Rev. *D
Page 11 of 19