CY62167G Datasheet, PDF (1/19 Pages) Cypress Semiconductor – 16-Mbit (1M Words × 16 Bit) Static RAM with Error-Correcting Code (ECC)

CY62167G Automotive
16-Mbit (1M Words × 16 Bit) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC)
Features
■ Ultra-low standby power
❐ Typical standby current: 5.5 A
❐ Maximum standby current: 75 A
■ High speed: 45 ns / 55 ns
■ Embedded error-correcting code (ECC) for single-bit error
correction
■ Temperature Ranges:
❐ Automotive-A: -40 C to +85 C
❐ Automotive-E: -40 C to +125 C
■ Operating voltage range: 2.2 V to 3.6 V
■ 1.0-V data retention
■ TTL-compatible inputs and outputs
■ Available in Pb-free 48-ball VFBGA and 48-pin TSOP I
packages
Functional Description
CY62167G is high-performance CMOS low-power (MoBL)
SRAM devices with embedded ECC. This device is offered in
dual chip-enable.
Devices with dual chip-enable are accessed by asserting both
chip-enable inputs – CE₁ as LOW and CE₂ as HIGH.
Data writes are performed by asserting the Write Enable input
(WE) LOW, and providing the data and address on device data
(I/O₀ through I/O₁₅) and address (A₀ through A₁₉) pins
respectively. The Byte High/Low Enable (BHE, BLE) inputs
control byte writes, and write data on the corresponding I/O lines
to the memory location specified. BHE controls I/O₈ through
I/O_15; BLE controls I/O₀ through I/O₇.
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on I/O lines (I/O₀ through I/O₁₅). Byte
accesses can be performed by asserting the required byte
enable signal (BHE, BLE) to read either the upper byte or the
lower byte of data from the specified address location.
All I/Os (I/O₀ through I/O₁₅) are placed in a HI-Z state when the
device is deselected (CE₁ HIGH / CE₂ LOW for dual chip-enable
device), or control signals are de-asserted (OE, BLE, and BHE).
These devices also have a unique “Byte Power down” feature
where if both the Byte Enables (BHE and BLE) are disabled, the
devices seamlessly switches to standby mode irrespective of the
state of the chip enable(s), thereby saving power.
The CY62167G device is available in a Pb-free 48-ball VFBGA
and 48-pin TSOP I packages. The device in the 48-pin TSOP I
package can also be configured to function as a 2 M words × 8
bit device.The logic block diagram is on page 2. Refer to Pin
Configurations on page 4 and the associated footnotes for
details.
Note
1. This device does not support automatic write-back on error detection.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-84902 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 12, 2016