CY14E064L_07 Datasheet, PDF (11/17 Pages) Cypress Semiconductor – 64 Kbit (8K x 8) nvSRAM

CY14E064L
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled ^{[4, 5, 14]}
t_RC
ADDRESS
DQ (DATA OUT)
t_AA
t_OH
DATA VALID
ADDRESS
CE
OE
DQ (DATA OUT)
ICC
Figure 6. SRAM Read Cycle 2: CE Controlled ^[4,14]
tRC
tLZCE
tACE
tPD
tHZCE
tDOE
tLZOE
STANDBY
t PU
ACTIVE
tHZOE
DATA VALID
Note
14. HSB must remain HIGH during READ and WRITE cycles.
Document Number: 001-06543 Rev. *D
Page 11 of 17
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