CY8C3246FNI-213T Datasheet, PDF (101/128 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C32 Family Data Sheet
11.7.5 External Memory Interface
Figure 11-53. Asynchronous Write and Read Cycle Timing, No Wait States
Tbus_clock
Bus Clock
EM_Addr
EM_CE
EM_WE
EM_OE
Twr_setup
EM_Data
Write Cycle
Minimum of 4 bus clock cycles between successive EMIF accesses
Table 11-53. Asynchronous Write and Read Timing Specifications^[56]
Parameter
Description
Fbus_clock Bus clock frequency^[57]
Tbus_clock Bus clock period^[58]
Twr_Setup Time from EM_data valid to rising edge of
EM_WE and EM_CE
Trd_setup Time that EM_data must be valid before rising
edge of EM_OE
Trd_hold
Time that EM_data must be valid after rising
edge of EM_OE
Conditions
Trd_setup
Trd_hold
Read Cycle
Min
Typ
–
–
30.3
–
Tbus_clock – 10 –
5
–
5
–
Max Units
33
MHz
–
ns
–
ns
–
ns
–
ns
Notes
56. Based on device characterization (Not production tested).
57. EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page 76.
58. EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency.
Document Number: 001-56955 Rev. *Y
Page 101 of 128