CY8C3246FNI-213T Datasheet, PDF (10/128 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PSoC^® 3: CY8C32 Family Data Sheet
Table 2-2 shows the pinout for the 72-pin CSP package. Since there are four V_DDIO pins, the set of I/O pins associated with any V_DDIO
may sink up to 100 mA total, same as for the 100-pin and 68-pin devices.
Table 2-2. CSP Pinout
Ball
Name
Ball
Name
Ball
Name
G6
P2[5]
F1
VDDD
A5
VDDA
E5
P2[6]
E1
VSSD
A6
VSSD
F5
P2[7]
E2
VCCD
B6
P12[2]
J7
P12[4]
C1
P15[0]
C6
P12[3]
H6
P12[5]
C2
P15[1]
A7
P0[0]
J6
VSSB
D2
P3[0]
B7
P0[1]
J5
Ind
D3
P3[1]
B5
P0[2]
H5
VBOOST
D4
P3[2]
C5
P0[3]
J4
VBAT
D5
P3[3]
A8
VIO0
H4
VSSD
B4
P3[4]
D6
P0[4]
J3
XRES_N
B3
P3[5]
D7
P0[5]
H3
P1[0]
A1
VIO3
C7
P0[6]
G3
P1[1]
B2
P3[6]
C8
P0[7]
H2
P1[2]
A2
P3[7]
E8
VCCD
J2
P1[3]
C3
P12[0]
F8
VSSD
G4
P1[4]
C4
P12[1]
G8
VDDD
G5
P1[5]
E3
P15[2]
E7
P15[4]
J1
VIO1
E4
P15[3]
F7
P15[5]
F4
P1[6]
B1^[10]
NC
G7
P2[0]
F3
P1[7]
B8^[10]
NC
H7
P2[1]
H1
P12[6]
D1^[10]
NC
H8
P2[2]
G1
P12[7]
D8^[10]
NC
F6
P2[3]
G2
P15[6]
A3
VCCA
E6
P2[4]
F2
P15[7]
A4
VSSA
J8
VIO2
Figure 2-7 and Figure 2-8 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog
performance on a two layer board.
 The two pins labeled VDDD must be connected together.
 The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-7 and Power System on
page 31. The trace between the two VCCD pins should be as short as possible.
 The two pins labeled VSSD must be connected together.
For information on circuit board layout issues for mixed signals, refer to the application note AN57821 - Mixed Signal Circuit Board
Layout Considerations for PSoC® 3 and PSoC 5.
Note
10. These pins are Do Not Use (DNU); they must be left floating.
Document Number: 001-56955 Rev. *Y
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