W158 Datasheet, PDF (10/12 Pages) Cypress Semiconductor – Spread Spectrum System Frequency Synthesizer

W158
2.5V AC Electrical Characteristics
T_A = 0°C to +70°C, V_DDQ3 = 3.3V±5%, V_DDQ2= 2.5V±5%
f_XTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.^[37]
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)
CPU = 133 MHz CPU = 100 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
t_P
Period
Measured on rising edge at 1.25V
7.5
7.65 10
10.2 ns
t_H
High Time
Duration of clock cycle above 2.0V
1.87
3.0
ns
t_L
Low Time
Duration of clock cycle below 0.4V
1.67
2.8
ns
t_R
Output Rise Edge Rate Measured from 0.4V to 2.0V
1
41
4 V/ns
t_F
Output Fall Edge Rate Measured from 2.0V to 0.4V
1
41
4 V/ns
t_D
Duty Cycle
Measured on rising and falling edge at 45
1.25V
55 45
55 %
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Max-
150
imum difference of cycle time between
two adjacent cycles.
150 ps
t_SK
Output Skew
Measured on rising edge at 1.25V
175
175 ps
f_ST
Frequency Stabiliza- Assumes full supply voltage reached
3
tion from Power-up
within 1 ms from power-up. Short cycles
(cold start)
exist prior to frequency stabilization.
3 ms
Z_o
AC Output Impedance Average value during switching transi-
20
tion. Used for determining series termi-
nation value.
20
Ω
CPUdiv2 Clock Outputs, CPUdiv2_0:1 (Lump Capacitance Test Load = 20 pF)
CPU = 133 MHz CPU = 100 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
t_P
Period
Measured on rising edge at 1.25V
15
15.3 20
20.4 ns
t_H
High Time
Duration of clock cycle above 2.0V
5.25
7.5
ns
t_L
Low Time
Duration of clock cycle below 0.4V
5.05
7.3
ns
t_R
Output Rise Edge Rate Measured from 0.4V to 2.0V
1
41
4 V/ns
t_F
Output Fall Edge Rate Measured from 2.0V to 0.4V
1
41
4 V/ns
t_D
Duty Cycle
Measured on rising and falling edge at 45
1.25V
55 45
55 %
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Max-
250
imum difference of cycle time between
two adjacent cycles.
250 ps
t_SK
Output Skew
Measured on rising edge at 1.25V
175
175 ps
f_ST
Frequency Stabiliza- Assumes full supply voltage reached
3
tion from Power-up
within 1 ms from power-up. Short cycles
(cold start)
exist prior to frequency stabilization.
3 ms
Z_o
AC Output Impedance Average value during switching transi-
20
tion. Used for determining series termi-
nation value.
20
Ω
Note:
37. Period, Jitter, offset, and skew measured on rising edge at 1.25V.
10