CY7C6471314 Datasheet, PDF (10/50 Pages) Cypress Semiconductor – EZ-USB FX1™ USB Microcontroller Full-speed USB Peripheral Controller

CY7C64713/14
At any given time, some RAM blocks are filling/emptying with
USB data under SIE control, while other RAM blocks are
available to the 8051 and/or the I/O control unit. The RAM
blocks operate as single-port in the USB domain, and dual-
port in the 8051-I/O domain. The blocks can be configured as
single, double, triple, or quad buffered as previously shown.
The I/O control unit implements either an internal-master (M
for master) or external-master (S for Slave) interface.
In Master (M) mode, the GPIF internally controls
FIFOADR[1..0] to select a FIFO. The RDY pins (two in the 56-
pin package, six in the 100-pin and 128-pin packages) can be
used as flag inputs from an external FIFO or other logic if
desired. The GPIF can be run from either an internally derived
clock or externally supplied clock (IFCLK), at a rate that
transfers data up to 96 Megabytes/s (48-MHz IFCLK with 16-
bit interface).
In Slave (S) mode, the FX1 accepts either an internally derived
clock or externally supplied clock (IFCLK, max. frequency 48
MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals
from external logic. When using an external IFCLK, the
external clock must be present before switching to the external
clock with the IFCLKSRC bit. Each endpoint can individually
be selected for byte or word operation by an internal configu-
ration bit, and a Slave FIFO Output Enable signal SLOE
enables data of the selected width. External logic must insure
that the output enable signal is inactive when writing data to a
slave FIFO. The slave interface can also operate asynchro-
nously, where the SLRD and SLWR signals act directly as
strobes, rather than a clock qualifier as in synchronous mode.
The signals SLRD, SLWR, SLOE and PKTEND are gated by
the signal SLCS#.
4.13.3 GPIF and FIFO Clock Rates
An 8051 register bit selects one of two frequencies for the
internally supplied interface clock: 30 MHz and 48 MHz. Alter-
natively, an externally supplied clock of 5 MHz–48 MHz
feeding the IFCLK pin can be used as the interface clock.
IFCLK can be configured to function as an output clock when
the GPIF and FIFOs are internally clocked. An output enable
bit in the IFCONFIG register turns this clock output off, if
desired. Another bit within the IFCONFIG register will invert
the IFCLK signal whether internally or externally sourced.
4.14 GPIF
The GPIF is a flexible 8- or 16-bit parallel interface driven by a
user-programmable finite state machine. It allows the
CY7C64713/4 to perform local bus mastering, and can
implement a wide variety of protocols such as ATA interface,
printer parallel port, and Utopia.
The GPIF has six programmable control outputs (CTL), nine
address outputs (GPIFADRx), and six general-purpose ready
inputs (RDY). The data bus width can be 8 or 16 bits. Each
GPIF vector defines the state of the control outputs, and deter-
mines what state a ready input (or multiple inputs) must be
before proceeding. The GPIF vector can be programmed to
advance a FIFO to the next data value, advance an address,
etc. A sequence of the GPIF vectors make up a single
waveform that will be executed to perform the desired data
move between the FX1 and the external device.
Document #: 38-08039 Rev. *B
4.14.1 Six Control OUT Signals
The 100- and 128-pin packages bring out all six Control Output
pins (CTL0-CTL5). The 8051 programs the GPIF unit to define
the CTL waveforms. The 56-pin package brings out three of
these signals, CTL0–CTL2. CTLx waveform edges can be
programmed to make transitions as fast as once per clock
(20.8 ns using a 48-MHz clock).
4.14.2 Six Ready IN Signals
The 100- and 128-pin packages bring out all six Ready inputs
(RDY0–RDY5). The 8051 programs the GPIF unit to test the
RDY pins for GPIF branching. The 56-pin package brings out
two of these signals, RDY0–1.
4.14.3 Nine GPIF Address OUT Signals
Nine GPIF address lines are available in the 100- and 128-pin
packages, GPIFADR[8..0]. The GPIF address lines allow
indexing through up to a 512-byte block of RAM. If more
address lines are needed, I/O port pins can be used.
4.14.4 Long Transfer Mode
In master mode, the 8051 appropriately sets GPIF transaction
count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or
GPIFTCB0) for unattended transfers of up to 2³² transactions.
The GPIF automatically throttles data flow to prevent under or
overflow until the full number of requested transactions
complete. The GPIF decrements the value in these registers
to represent the current status of the transaction.
4.15 ECC Generation
The EZ-USB FX1 can calculate ECCs (Error-Correcting
Codes) on data that passes across its GPIF or Slave FIFO
interfaces. There are two ECC configurations: Two ECCs,
each calculated over 256 bytes (SmartMedia™ Standard); and
one ECC calculated over 512 bytes.
The ECC can correct any one-bit error or detect any two-bit
error.
Note: To use the ECC logic, the GPIF or Slave FIFO interface
must be configured for byte-wide operation.
4.15.1 ECC Implementation
The two ECC configurations are selected by the ECCM bit:
4.15.1.1 ECCM = 0
Two 3-byte ECCs, each calculated over a 256-byte block of
data. This configuration conforms to the SmartMedia
Standard.
Write any value to ECCRESET, then pass data across the
GPIF or Slave FIFO interface. The ECC for the first 256 bytes
of data will be calculated and stored in ECC1. The ECC for the
next 256 bytes will be stored in ECC2. After the second ECC
is calculated, the values in the ECCx registers will not change
until ECCRESET is written again, even if more data is subse-
quently passed across the interface.
4.15.1.2 ECCM=1
One 3-byte ECC calculated over a 512-byte block of data.
Write any value to ECCRESET then pass data across the
GPIF or Slave FIFO interface. The ECC for the first 512 bytes
of data will be calculated and stored in ECC1; ECC2 is unused.
After the ECC is calculated, the value in ECC1 will not change
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