CY7C1440AV33_12 Datasheet, PDF (10/33 Pages) Cypress Semiconductor – 36-Mbit (1 M × 36) Pipelined Sync SRAM

CY7C1440AV33
Truth Table for Read/Write
The truth table for Read/Write for CY7C1440AV33 follows. ^{[8, 9, 10]}
Function (CY7C1440AV33)
GW
Read
H
Read
H
Write byte A – (DQ_A and DQP_A)
H
Write byte B – (DQ_B and DQP_B)
H
Write bytes B, A
H
Write byte C – (DQ_C and DQP_C)
H
Write bytes C, A
H
Write bytes C, B
H
Write bytes C, B, A
H
Write byte D – (DQ_D and DQP_D)
H
Write bytes D, A
H
Write bytes D, B
H
Write bytes D, B, A
H
Write bytes D, C
H
Write bytes D, C, A
H
Write bytes D, C, B
H
Write all bytes
H
Write all bytes
L
BWE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
BW_D
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
BW_C
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
BW_B
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
X
BW_A
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
Notes
8. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
9.
aBtWth^xeresparmeseetnimtseafnoyr
byte write
any given
signal.
write.
To
enable
any
byte
write
BW_x,
a
Logic
LOW
signal
should
be
applied
at
clock
rise.
Any
number
of
bye
writes
can
be
enabled
10. Table only lists a partial listing of the byte write combinations. Any combination of BW_X is valid. Appropriate write will be done based on which byte write is active.
Document Number: 38-05383 Rev. *K
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