CY7C1440AV33_12 Datasheet, PDF (1/33 Pages) Cypress Semiconductor – 36-Mbit (1 M × 36) Pipelined Sync SRAM

CY7C1440AV33
36-Mbit (1 M × 36) Pipelined Sync SRAM
36-Mbit (1 M × 36) Pipelined Sync SRAM
Features
■ Supports bus operation up to 250 MHz
■ Available speed grades are 250 and 167 MHz
■ Registered inputs and outputs for pipelined operation
■ 3.3 V core power supply
■ 2.5 V/3.3 V I/O power supply
■ Fast clock-to-output times
❐ 2.6 ns (for 250-MHz device)
■ Provide high-performance 3-1-1-1 access rate
■ User-selectable burst counter supporting Intel^ Pentium^
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Single cycle chip deselect
■ CY7C1440AV33 available in Pb-free 100-pin TQFP package,
Pb-free 165-ball FBGA package.
■ IEEE 1149.1 JTAG-compatible boundary scan
■ “ZZ” sleep mode option
Functional Description
The CY7C1440AV33 SRAM integrates 1 M × 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE₁), depth-expansion
chip enables (CE₂ and CE₃), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW_X and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see pin descriptions and truth table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active _LOW
causes all bytes to be written.
The CY7C1440AV33 operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
250 MHz
2.6
475
120
167 MHz Unit
3.4
ns
375
mA
120
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05383 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 14, 2012