CY7C1416AV18 Datasheet, PDF (10/24 Pages) Cypress Semiconductor – 36-Mbit DDR-II SRAM 2-Word Burst Architecture

PRELIMINARY
CY7C1416AV18
CY7C1427AV18
CY7C1418AV18
CY7C1420AV18
Write Cycle Descriptions (CY7C1416AV18 and CY7C1418AV18)^{[2, 8]}
BWS_0,NWS₀ BWS_1,NWS₁ K
K
Comments
L
L
L-H – During the Data portion of a Write sequence:
CY7C1416AV18 − both nibbles (D_[7:0]) are written into the device,
CY7C1418AV18 − both bytes (D_[17:0]) are written into the device.
L
L
– L-H During the Data portion of a Write sequence:
CY7C1416AV18 − both nibbles (D_[7:0]) are written into the device,
CY7C1418AV18 − both bytes (D_[17:0]) are written into the device.
L
H
L-H – During the Data portion of a Write sequence:
CY7C1416AV18 − only the lower nibble (D_[3:0]) is written into the device. D_[7:4]
will remain unaltered,
CY7C1418AV18 − only the lower byte (D_[8:0]) is written into the device. D_[17:9]
will remain unaltered.
L
H
– L-H During the Data portion of a Write sequence:
CY7C1416AV18 − only the lower nibble (D_[3:0]) is written into the device. D_[7:4]
will remain unaltered,
CY7C1418AV18 − only the lower byte (D_[8:0]) is written into the device. D_[17:9]
will remain unaltered.
H
L
L-H – During the Data portion of a Write sequence:
CY7C1416AV18 − only the upper nibble (D_[7:4]) is written into the device. D_[3:0]
will remain unaltered,
CY7C1418AV18 − only the upper byte (D_[17:9]) is written into the device. D_[8:0]
will remain unaltered.
H
L
– L-H During the Data portion of a Write sequence:
CY7C1416AV18 − only the upper nibble (D_[7:4]) is written into the device. D_[3:0]
will remain unaltered,
CY7C1418AV18 − only the upper byte (D_[17:9]) is written into the device. D_[8:0]
will remain unaltered.
H
H
L-H – No data is written into the devices during this portion of a Write operation.
H
H
– L-H No data is written into the devices during this portion of a Write operation.
Write Cycle Descriptions^{[2, 8]} (CY7C1420AV18)
BWS₀ BWS₁ BWS₂ BWS₃ K
L
L
L
L
L-H
K
Comments
– During the Data portion of a Write sequence, all four bytes (D_[35:0]) are
written into the device.
L
L
L
L
–
L-H During the Data portion of a Write sequence, all four bytes (D_[35:0]) are
written into the device.
L
H
H
H
L-H
– During the Data portion of a Write sequence, only the lower byte (D_[8:0]) is
written into the device. D_[35:9] will remain unaltered.
L
H
H
H
–
L-H During the Data portion of a Write sequence, only the lower byte (D_[8:0]) is
written into the device. D_[35:9] will remain unaltered.
H
L
H
H
L-H
– During the Data portion of a Write sequence, only the byte (D_[17:9]) is
written into the device. D_[8:0] and D_[35:18] will remain unaltered.
H
L
H
H
–
L-H During the Data portion of a Write sequence, only the byte (D_[17:9]) is
written into the device. D_[8:0] and D_[35:18] will remain unaltered.
H
H
L
H
L-H
– During the Data portion of a Write sequence, only the byte (D_[26:18]) is
written into the device. D_[17:0] and D_[35:27] will remain unaltered.
H
H
L
H
–
L-H During the Data portion of a Write sequence, only the byte (D_[26:18]) is
written into the device. D_[17:0] and D_[35:27] will remain unaltered.
H
H
H
L
L-H
During the Data portion of a Write sequence, only the byte (D_[35:27]) is
written into the device. D_[26:0] will remain unaltered.
Note:
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS₀, NWS₁, BWS₀, BWS₁, BWS₂, and BWS₃ can be altered on different
portions of a Write cycle, as long as the set-up and hold requirements are achieved.
Document Number: 38-05616 Rev. **
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