CY7C1344F Datasheet, PDF (10/15 Pages) Cypress Semiconductor – 2-Mbit (64K x 36) Flow-Through Sync SRAM

CY7C1344F
Timing Diagrams
Read Cycle Timing^[16]
tCYC
CLK
ADSP
ADSC
t _CH t _CL
tADS tADH
tADS tADH
tAS tAH
ADDRESS
GW, BWE,BW
[A:D]
CE
ADV
A1
A2
t _{WES tWEH}
tCES tCEH
t
ADVS
tADVH
ADV suspends burst.
Deselect Cycle
OE
Data Out (Q)
tOEV
High-Z
tCLZ
tCDV
tOEHZ
Q(A1)
Single READ
tOELZ
tCDV
tDOH
Q(A2) Q(A2 + 1)
Q(A2 + 2)
BURST
READ
tCHZ
Q(A2 + 3)
Q(A2) Q(A2 + 1) Q(A2 + 2)
Burst wraps around
to its initial state
DON’T CARE UNDEFINED
Note:
16. On this diagram, when CE is LOW, CE₁ is LOW, CE₂ is HIGH and CE₃ is LOW. When CE is HIGH, CE₁ is HIGH or CE₂ is LOW or CE₃ is HIGH.
Document #: 38-05432 Rev. *A
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