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| CY7C09159AV_11 Datasheet, PDF (10/19 Pages) Cypress Semiconductor – 3.3-V 8 K × 9 Synchronous Dual Port Static RAM | |||
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CY7C09159AV
Switching Waveforms (continued)
Figure 5. Pipelined Read-to-Write-to-Read (OE = VIL)[14, 15, 16, 17]
tCYC2
tCH2
tCL2
CLK
CE0
tSC
CE1
R/W
tSW
ADDRESS
tSA
DATAIN
DATAOUT
CLK
tHC
tSW
tHW
tHW
An
tHA
An+1
An+2
tCD2
tCKHZ
Qn
An+2
tSD tHD
Dn+2
An+3
tCKLZ
An+4
tCD2
Qn+3
READ
NO OPERATION
WRITE
READ
Figure 6. Pipelined Read-to-Write-to-Read (OE Controlled)[14, 15, 16, 17]
tCYC2
tCH2
tCL2
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW
tHW
An
ADDRESS
tSA
tHA
DATAOUT
DATAIN
An+1
tCD2
An+2
tSD tHD
Dn+2
Qn
tOHZ
An+3
Dn+3
An+4
An+5
tCKLZ
tCD2
Qn+4
OE
READ
WRITE
READ
Notes
14. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only
15. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
16. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
17. During âNo operation,â data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Document Number: 38-06053 Rev. *E
Page 10 of 19
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