CY7C09159AV_11 Datasheet, PDF (1/19 Pages) Cypress Semiconductor – 3.3-V 8 K × 9 Synchronous Dual Port Static RAM

CY7C09169AVTITLE
CY7C09159AV
3.3-V 8 K × 9
Synchronous Dual Port Static RAM
Features
■ True dual-ported memory cells which allow simultaneous
access of the same memory location
■ Flow-through/Pipelined device
❐ 8 K × 9 organization (CY7C09159AV)
■ Three Modes
❐ Flow-through
❐ Pipelined
❐ Burst
■ Pipelined output mode on both ports allows fast 67-MHz
operation
■ 0.35-micron complementary metal oxide semiconductor
(CMOS) for optimum speed/power
■ High-speed clock to data access 9 ns (max.)
Logic Block Diagram
■ 3.3 V Low operating power
❐ Active = 135 mA (typical)
❐ Standby = 10 μA (typical)
■ Fully synchronous interface for easier operation
■ Burst counters increment addresses internally
❐ Shorten cycle times
❐ Minimize bus noise
❐ Supported in Flow-through and Pipelined modes
■ Dual chip enables for easy depth expansion
■ Automatic power-down
■ Commercial temperature ranges
■ Available in 100-pin thin quad plastic flatpack (TQFP)
■ Pb-free packages available
R/W_L
OE_L
R/W_R
OE_R
CE_0L
1
CE_1L
0
0/1
1
CE_0R
0
CE_1R
0/1
FT/Pipe_L
I/O_0L−I/O_8L
1
0
0/1
9
A₀−A_12L
CLK_L
ADS_L
CNTEN_L
CNTRST_L
13
Counter/
Address
Register
Decode
I/O
Control
I/O
Control
True Dual-Ported
RAM Array
0
1
0/1
9
FT/Pipe_R
I/O_0R−I/O_8R
13
Counter/
Address
Register
Decode
A₀−A_12R
CLK_R
ADS_R
CNTEN_R
CNTRST_R
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06053 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 8, 2011