CY28443-2 Datasheet, PDF (10/24 Pages) Cypress Semiconductor – Clock Generator for Intel® Calistoga Chipset

PRELIMINARY
CY28443-2
Byte 14: Control Register 14 (continued)
Bit
3
@Pup
0
Name
CLKREQ#A
2
0
CLKREQ#A
1
0
CLKREQ#A
0
0
CLKREQ#A
Description
SRC[T/C]4 Control
0 = SRC[T/C]4 not stoppable by CLKREQ#A
1 = SRC[T/C]4 stoppable by CLKREQ#A
SRC[T/C]3 Control
0 = SRC[T/C]3 not stoppable by CLKREQ#A
1 = SRC[T/C]3 stoppable by CLKREQ#A
SRC[T/C]2 Control
0 = SRC[T/C]2 not stoppable by CLKREQ#A
1 = SRC[T/C]2 stoppable by CLKREQ#A
SRC[T/C]1 Control
0 = SRC[T/C]1 not stoppable by CLKREQ#A
1 = SRC[T/C]1 stoppable by CLKREQ#A
Byte 15: Control Register 15
Bit
7
@Pup
1
Name
CLKREQ#B
6
0
RESERVED
5
0
RESERVED
4
0
CLKREQ#B
3
0
CLKREQ#B
2
0
CLKREQ#B
1
0
CLKREQ#B
0
0
CLKREQ#B
Description
SRC[T/C]8 Control
0 = SRC[T/C]8 not stoppable by CLKREQ#B
1 = SRC[T/C]8 stoppable by CLKREQ#B
RESERVED
RESERVED
SRC[T/C]5 Control
0 = SRC[T/C]5 not stoppable by CLKREQ#B
1= SRC[T/C]5 stoppable by CLKREQ#B
SRC[T/C]4 Control
0 = SRC[T/C]4 not stoppable by CLKREQ#B
1= SRC[T/C]4 stoppable by CLKREQ#B
SRC[T/C]3 Control
0 = SRC[T/C]3 not stoppable by CLKREQ#B
1= SRC[T/C]3 stoppable by CLKREQ#B
SRC[T/C]2 Control
0 = SRC[T/C]2 not stoppable by CLKREQ#B
1= SRC[T/C]2 stoppable by CLKREQ#B
SRC[T/C]1 Control
0 = SRC[T/C]1 not stoppable by CLKREQ#B
1= SRC[T/C]1 stoppable by CLKREQ#B
Table 5. Crystal Recommendations
Frequency
(Fund)
14.31818 MHz
Cut Loading Load Cap
AT Parallel 20 pF
Drive
(max.)
0.1 mW
Shunt Cap
(max.)
5 pF
Motional
(max.)
0.016 pF
Tolerance
(max.)
35 ppm
Stability
(max.)
30 ppm
Aging
(max.)
5 ppm
The CY28443-2 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28443-2 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Document #: 38-07718 Rev. *B
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