CY14C512Q_12 Datasheet, PDF (10/32 Pages) Cypress Semiconductor – 512-Kbit (64 K × 8) SPI nvSRAM

CY14C512Q
CY14B512Q
CY14E512Q
Status Register
The Status Register bits are listed in Table 3. The Status Register
consists of a Ready bit (RDY) and data protection bits BP1, BP0,
WEN, and WPEN. The RDY bit can be polled to check the Ready
or Busy status while a nvSRAM STORE or Software RECALL
cycle is in progress. The Status Register can be modified by
WRSR instruction and read by RDSR or FAST_RDSR
instruction. However, only the WPEN, BP1, and BP0 bits of the
Status Register can be modified by using the WRSR instruction.
The WRSR instruction has no effect on WEN and RDY bits. The
default value shipped from the factory for WEN, BP0, BP1, bits
4 -5, SNL and WPEN is ‘0’.
SNL (bit 6) of the Status Register is used to lock the serial
number written using the WRSN instruction. The serial number
can be written using the WRSN instruction multiple times while
this bit is still '0'. When set to '1', this bit prevents any modification
to the serial number. This bit is factory programmed to '0' and can
only be written to once. After this bit is set to '1', it can never be
cleared to '0'.
Table 3. Status Register Format
Bit 7
WPEN (0)
Bit 6
SNL (0)
Bit 5
X (0)
Bit 4
X (0)
Bit 3
BP1 (0)
Bit 2
BP0 (0)
Bit 1
WEN (0)
Bit 0
RDY
Table 4. Status Register Bit Definition
Bit
Bit 0 (RDY)
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Bit 4-5
Bit 6 (SNL)
Bit 7 (WPEN)
Definition
Description
Ready
Read only bit indicates the ready status of device to perform a memory access. This bit is
set to ‘1’ by the device while a STORE or Software RECALL cycle is in progress.
Write Enable
WEN indicates if the device is write enabled. This bit defaults to ‘0’ (disabled) on power-up.
WEN = '1' --> Write enabled
WEN = '0' --> Write disabled
Block Protect bit ‘0’
Used for block protection. For details see Table 5 on page 12.
Block Protect bit ‘1’
Used for block protection. For details see Table 5 on page 12.
Don’t care
These bits are non-writable and always return ‘0’ upon read.
Serial Number Lock Set to '1' for locking serial number
Write Protect Enable bit Used for enabling the function of Write Protect Pin (WP). For details see Table 6 on page
12.
Read Status Register (RDSR) Instruction
The Read Status Register instruction provides access to the
Status Register at SPI frequency up to 40 MHz. This instruction
is used to probe the Write Enable status of the device or the
Ready status of the device. RDY bit is set by the device to 1
whenever a STORE or Software RECALL cycle is in progress.
The block protection and WPEN bits indicate the extent of
protection employed.
This instruction is issued after the falling edge of CS using the
opcode for RDSR.
Fast Read Status Register (FAST_RDSR) Instruction
The FAST_RDSR instruction allows you to read the Status
Register at a SPI frequency above 40 MHz and up to 104 MHz
(max).This instruction is used to probe the Write Enable status
of the device or the Ready status of the device. RDY bit is set by
the device to 1 whenever a STORE or Software RECALL cycle
is in progress. The block protection and WPEN bits indicate the
extent of protection employed.
This instruction is issued after the falling edge of CS using the
opcode for RDSR followed by a dummy byte.
Write Status Register (WRSR) Instruction
The WRSR instruction enables the user to write to the Status
Register. However, this instruction cannot be used to modify bit
0 (RDY), bit 1 (WEN) and bits 4-5. The BP0 and BP1 bits can be
used to select one of four levels of block protection. Further,
WPEN bit must be set to ‘1’ to enable the use of Write Protect
(WP) pin.
WRSR instruction is a write instruction and needs writes to be
enabled (WEN bit set to ‘1’) using the WREN instruction before
it is issued. The instruction is issued after the falling edge of CS
using the opcode for WRSR followed by eight bits of data to be
stored in the Status Register. WRSR instruction can be used to
modify only bits 2, 3, 6 and 7 of the Status Register.
Note In CY14X512Q, the values written to Status Register are
saved to nonvolatile memory only after a STORE operation. If
AutoStore is disabled (or while using CY14X512Q1A), any
modifications to the Status Register must be secured by
performing a Software STORE operation.
Note CY14X512Q2A does not have WP pin. Any modification to
bit 7 of the Status Register has no effect on the functionality of
CY14X512Q2A.
Document Number: 001-65267 Rev. *D
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