CY14C512Q_12 Datasheet, PDF (1/32 Pages) Cypress Semiconductor – 512-Kbit (64 K × 8) SPI nvSRAM

CY14C512Q
CY14B512Q
CY14E512Q
512-Kbit (64 K × 8) SPI nvSRAM
512-Kbit (64 K × 8) SPI nvSRAM
Features
■ 512-Kbit nonvolatile static random access memory (nvSRAM)
internally organized as 64 K × 8
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using SPI
instruction (Software STORE) or HSB pin (Hardware
STORE)
❐ RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
❐ Support automatic STORE on power-down with a small
capacitor (except for CY14X512Q1A)
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1million STORE cycles to QuantumTrap
❐ Data retention: 20 years at 85 C
■ 40-MHz, and 104-MHz High-speed serial peripheral interface
(SPI)
❐ 40-MHz clock rate SPI write and read with zero cycle delay
❐ 104-MHz clock rate SPI write and SPI read (with special fast
read instructions)
❐ Supports SPI mode 0 (0,0) and mode 3 (1,1)
■ SPI access to special functions
❐ Nonvolatile STORE/RECALL
❐ 8-byte serial number
❐ Manufacturer ID and Product ID
❐ Sleep mode
■ Write protection
❐ Hardware protection using Write Protect (WP) pin
❐ Software protection using Write Disable instruction
❐ Software block protection for 1/4, 1/2, or entire array
■ Low power consumption
❐ Average active current of 3 mA at 40 MHz operation
❐ Average standby mode current of 150 A
❐ Sleep mode current of 8 A
■ Industry standard configurations
❐ Operating voltages:
• CY14C512Q: V_CC = 2.4 V to 2.6 V
• CY14B512Q: V_CC = 2.7 V to 3.6 V
• CY14E512Q: V_CC = 4.5 V to 5.5 V
❐ Industrial temperature
❐ 8- and 16-pin small outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
Functional Overview
The Cypress CY14X512Q combines a 512-Kbit nvSRAM^[1] with
a nonvolatile element in each memory cell with serial SPI
interface. The memory is organized as 64 K words of 8 bits each.
The embedded nonvolatile elements incorporate the
QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile elements (STORE operation) takes place automati-
cally at power-down (except for CY14X512Q1A). On power-up,
data is restored to the SRAM from the nonvolatile memory
(RECALL operation). You can also initiate the STORE and
RECALL operations through SPI instruction.
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14X512Q1A CY14X512Q2A CY14X512Q3A
No
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Logic Block Diagram
VCC VCAP
Serial Number
8x8
SI
CS
SCK
WP
SO
Power Control
Block
SLEEP
SPI Control Logic
Write Protection
Instruction decoder
Manufacturer ID /
Product ID
RDSN/WRSN/RDID
READ/WRITE
STORE/RECALL/ASENB/ASDISB
Memory
Data &
Address
Control
QuantumTrap
64 K x 8
SRAM
64 K x 8
STORE
RECALL
WRSR/RDSR/WREN
Status Register
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-65267 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 24, 2012