S29PL-J Datasheet, PDF (1/101 Pages) SPANSION – CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control

S29PL-J
128-/128-/64-/32-Mbit (8/8/4/2M x 16-Bit)
3V, Flash with Enhanced VersatileIO™
Distinctive Characteristics
Architectural Advantages
 128-/128-/64-/32-Mbit Page Mode devices
– Page size of 8 words: Fast page read access from random
locations within the page
 Single power supply operation
– Full Voltage range: 2.7 to 3.6 V read, erase, and program
operations for battery-powered applications
 Dual Chip Enable inputs (only in PL129J)
– Two CE# inputs control selection of each half of the
memory space
 Simultaneous Read/Write Operation
– Data can be continuously read from one bank while
executing erase/program functions in another bank
– Zero latency switching from write to read operations
 FlexBank Architecture (PL127J/PL064J/PL032J)
– 4 separate banks, with up to two simultaneous operations
per device
– Bank A:
PL127J -16 Mbit (4 Kw  8 and 32 Kw  31)
PL064J - 8 Mbit (4 Kw  8 and 32 Kw  15)
PL032J - 4 Mbit (4 Kw  8 and 32 Kw  7)
– Bank B:
PL127J - 48 Mbit (32 Kw  96)
PL064J - 24 Mbit (32 Kw  48)
PL032J - 12 Mbit (32 Kw  24)
– Bank C:
PL127J - 48 Mbit (32 Kw  96)
PL064J - 24 Mbit (32 Kw  48)
PL032J - 12 Mbit (32 Kw  24)
– Bank D:
PL127J -16 Mbit (4 Kw  8 and 32 Kw  31)
PL064J - 8 Mbit (4 Kw  8 and 32 Kw  15)
PL032J - 4 Mbit (4 Kw  8 and 32 Kw  7)
 FlexBank Architecture (PL129J)
– 4 separate banks, with up to two simultaneous operations
per device
– CE#1 controlled banks:
Bank 1A: PL129J - 16-Mbit (4Kw  8 and 32Kw  31)
Bank 1B: PL129J - 48-Mbit (32Kw  96)
– CE#2 controlled banks:
Bank 2A: PL129J - 48-Mbit (32 Kw  96)
Bank 2B: PL129J - 16-Mbit (4 Kw  8 and 32 Kw  31)
 Enhanced VersatileI/O (V_IO) Control
– Output voltage generated and input voltages tolerated on
all control inputs and I/Os is determined by the voltage on
the V_IO pin
– V_IO options at 1.8 V and 3 V I/O for PL127J and PL129J
devices
– 3V V_IO for PL064J and PL032J devices
 Secured Silicon Sector region
– Up to 128 words accessible through a command sequence
– Up to 64 factory-locked words
– Up to 64 customer-lockable words
 Both top and bottom boot blocks in one device
 Manufactured on 110-nm process technology
 Data Retention: 20 years typical
 Cycling Endurance: 1 million cycles per sector typical
Performance Characteristics
 High Performance
– Page access times as fast as 20 ns
– Random access times as fast as 55 ns
 Power consumption (typical values at 10 MHz)
– 45 mA active read current
– 17 mA program/erase current
– 0.2 A typical standby mode current
Software Features
 Software command-set compatible with JEDEC 42.4
standard
– Backward compatible with Am29F, Am29LV, Am29DL, and
AM29PDL families and MBM29QM/RM, MBM29LV,
MBM29DL, MBM29PDL families
 CFI (Common Flash Interface) compliant
– Provides device-specific information to the system,
allowing host software to easily reconfigure for different
Flash devices
 Erase Suspend / Erase Resume
– Suspends an erase operation to allow read or program
operations in other sectors of same bank
 Program Suspend / Program Resume
– Suspends a program operation to allow read operation
from sectors other than the one being programmed
 Unlock Bypass Program command
 Reduces overall programming time when issuing multiple
program command sequences
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00615 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 10, 2016