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MB9D560 Datasheet, PDF (1/91 Pages) SPANSION – This document states the current technical specifications regarding | |||
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MB9D560 Series
32-bit Microcontroller
TraveoTM Family
MB9D560 series has Cypress 32-bit microcontrollers for automobile motor control. They use the ARM® Cortex-R5 MPCoreTM CPU
that is compatible with the ARM family.
Notes:
⢠ARM, Cortex, Thumb are the registered trademarks of ARM Limited in the EU and other countries.
⢠MPCore, CoreSight are the trademarks of ARM Limited in the EU and other countries.
Features
Technology
ï®CMOS 90nm technology
CPU
ï®ARM Cortex®-R5F
ï®32-bit ARM architecture
ï®2-instruction issuance super scalar
ï®8-stage pipeline
ï®ARMv7 / Thumb®-2 instruction set
ï®Floating-Point Unit (FPU)
ï¯ Double precision
ï®Memory protection Unit (MPU)
ï¯ 16 area
ï®ECC support for the TCM port
ï¯ 1-bit error correction, 2-bit error detection ECC (SEC-DED)
ï®TCM port
ï¯ 2 TCM ports
ï®ATCM port
ï®BTCM 2 ports (B0TCM, B1TCM)
ï®VIC port
ï¯ Low latency interrupt
ï®AXI master interface
ï¯ 64-bit AXI interface (instruction / data access)
ï¯ 32-bit AXI interface (I/O access)
ï®AXI slave interface
ï¯ 64-bit AXI interface (accessible to TCM port)
ï®CPU configuration
ï¯ 2 CPUs (AMP operation)
ï®Operating frequency
ï¯ Maximum 200 MHz
ï®Trace with ETM-R5
Debugging
ï®ARM CoreSightTM Technology
ï¯ Each CPU embedded Embedded Trace Macro (ETM),
trace support of CPU operation
ï®Debugging interface
ï¯ JTAG (5 pin )
ï¯ Support clock : maximum 20 MHz
ï®Debugging security support
ï¯ 128-bit security key (Device security key)
ï®Wakeup function on JTAG
Operation mode
ï®User mode
ï¯ Normal mode (internal memory activation)
ï®Serial writer mode
Clock control
ï®Internal clock source
ï¯ Fast-CR oscillation (8 MHz)
ï¯ Slow-CR oscillation (100 kHz)
ï®External oscillation input
ï¯ Main clock input
ï®Embedded PLL
ï¯ Main PLL (Multiplying clock of main oscillation )
ï®Oscillator stabilized timer
ï¯ Support oscillator stabilized timer for all clock source
independently
ï¯ After a lapse of oscillator stabilized time, it is able to use
source clock timer (Except PLL for FlexRay/RDC)
Cypress Semiconductor Corporation â¢
Document Number: 002-05679 Rev.*A
198 Champion Court ⢠San Jose, CA 95134-1709 ⢠408-943-2600
Revised March 22, 2016
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