CY7C373 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – UltraLogic™ 64-Macrocell Flash CPLD

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CY7C373i
UltraLogic™ 64-Macrocell Flash CPLD
Features
• 64 macrocells in four logic blocks
• 64 I/O pins
• 5 dedicated inputs including 4 clock pins
• In-System Reprogrammable™ (ISR™) Flash
technology
— JTAG interface
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
— f_MAX = 125 MHz
— t_PD = 10 ns
— t_S = 5.5 ns
— t_CO = 6.5 ns
• Fully PCI compliant
• 3.3V or 5.0V I/O operation
• Available in 84-pin PLCC and 100-pin TQFP packages
• Pin compatible with the CY7C374i
Functional Description
The CY7C373i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C373i is
designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic™ FLASH370i devices, the CY7C373i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins.The ISR interface is enabled
using the programming voltage pin (ISR_EN). Additionally,
because of the superior routability of the FLASH370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
Logic Block Diagram
CLOCK
INPUT _INPUTS
16 I/Os
I/O₀-I/O₁₅
1
INPUT
MACROCELL
2
4
INPUT/CLOCK
MACROCELLS
2
LOGIC
BLOCK
36
A
16
LOGIC
PIM
36
BLOCK
D
16
16 I/Os
I/O₄₈−I/O₆₃
16 I/Os
I/O₁₆-I/O₃₁
LOGIC
BLOCK
36
B
16
LOGIC
36
BLOCK
C
16
16 I/Os
I/O₃₂−I/O₄₇
32
32
Selection Guide
7C373i–125 7C373i–100 7C373i–83
Maximum Propagation Delay^[1], t_PD (ns)
10
12
15
Minimum Set-up, t_S (ns)
5.5
6.0
8
Maximum Clock to Output^[1], t_CO (ns)
6.5
6.5
8
Typical Supply Current, I_CC (mA)
75
75
75
Note:
1. The 3.3V I/O mode timing adder, t_3.3IO, must be added to this specification when V_CCIO = 3.3V.
7C373iL-83
15
8
8
45
7C373i–66
20
10
10
75
7C373iL–66
20
10
10
45
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-03030 Rev. *A
Revised April 8, 2004