CY7C185_06 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 8K x 8 Static RAM

1bCY7C185
CY7C185
Features
• High speed
— 15 ns
• Fast t_DOE
• Low active power
— 715 mW
• Low standby power
— 85 mW
• CMOS for optimum speed/power
• Easy memory expansion with CE₁, CE₂ and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in non Pb-free 28-pin (300-Mil) Molded SOJ,
28-pin (300-Mil) Molded SOIC and both Pb-free and non
Pb-free in 28-pin (300-Mil) Molded DIP
Logic Block Diagram
8K x 8 Static RAM
Functional Description^[1]
The CY7C185 is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE₁), an active
HIGH chip enable (CE₂), and active LOW output enable (OE)
and tri-state drivers. This device has an automatic
power-down feature (CE₁ or CE₂), reducing the power
consumption by 70% when deselected. The CY7C185 is in a
standard 300-mil-wide DIP, SOJ, or SOIC package.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE₁ and WE
inputs are both LOW and CE₂ is HIGH, data on the eight data
input/output pins (I/O₀ through I/O₇) is written into the memory
location addressed by the address present on the address
pins (A₀ through A₁₂). Reading the device is accomplished by
selecting the device and enabling the outputs, CE₁ and OE
active LOW, CE₂ active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins are present on
the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
CE₁
CE₂
WE
OE
INPUT BUFFER
8K x 8
ARRAY
POWER
COLUMN DECODER ^DOWN
Pin Configurations
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
DIP/SOJ
Top View
NC ₁
A_{4 2}
A_{5 3}
A_{6 4}
A_{7 5}
A_{8 6}
A9 ₇
A_{10 8}
A_{11 9}
A_{12 10}
I/O_{0 11}
I/O_{1 12}
I/O_{2 13}
GND ₁₄
28 ^VCC
27 ^WE
26 ^CE2
25 ^A3
24 ^A2
23 ^A1
22 ^OE
21 ^A0
20 ^CE1
19 ^I/O7
18 ^I/O6
17 ^I/O5
16 ^I/O4
15 ^I/O3
Selection Guide
-15
-20
-25
-35
Maximum Access Time (ns)
15
20
25
35
Maximum Operating Current (mA)
130
110
100
100
Maximum CMOS Standby Current (mA)
15
15
15
15
Notes:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05043 Rev. *B
Revised July 24, 2006
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