CY7C1566V18_08 Datasheet, PDF (1/28 Pages) Cypress Semiconductor – 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18
72-Mbit DDR-II+ SRAM 2-Word Burst
Architecture (2.5 Cycle Read Latency)
Features
■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
■ 400 MHz clock for high bandwidth
■ 2-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces
(data transferred at 800 MHz) at 400 MHz
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ Core V_DD = 1.8V ± 0.1V; IO V_DDQ = 1.4V to V_DD ^[1]
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C1566V18 – 8M x 8
CY7C1577V18 – 8M x 9
CY7C1568V18 – 4M x 18
CY7C1570V18 – 2M x 36
Functional Description
The CY7C1566V18, CY7C1577V18, CY7C1568V18, and
CY7C1570V18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of K and K. Each address location is associated with two 8-bit
words (CY7C1566V18), 9-bit words (CY7C1577V18), 18-bit
words (CY7C1568V18), or 36-bit words (CY7C1570V18) that
burst sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
400 MHz
400
x8
1400
x9
1400
x18
1400
x36
1400
375 MHz
375
1300
1300
1300
1300
333 MHz
333
1200
1200
1200
1200
300 MHz
300
1100
1100
1100
1100
Unit
MHz
mA
Note
1. The QDR consortium specification for V_DDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V_DDQ
= 1.4V to V_DD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-06551 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 11, 2008
[+] Feedback