CY7C1351G_13 Datasheet, PDF (1/21 Pages) Cypress Semiconductor – 4-Mbit (128 K x 36) Flow-Through SRAM with NoBL™ Architecture

CY7C1351G
4-Mbit (128 K × 36) Flow-Through SRAM
with NoBL™ Architecture
4-Mbit (128 K × 36) Flow-Through SRAM with NoBL™ Architecture
Features
■ Can support up to 133-MHz bus operations with zero wait
states
❐ Data is transferred on every clock
■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self-timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow-through operation
■ Byte write capability
■ 128 K × 36 common I/O architecture
■ 2.5 V/3.3 V I/O power supply (V_DDQ)
■ Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Available in Pb-free 100-pin TQFP package
■ Burst capability – linear or interleaved burst order
■ Low standby power
Functional Description
The CY7C1351G is a 3.3 V, 128 K × 36 synchronous
flow-through burst SRAM designed specifically to support
unlimited true back-to-back read/write operations without the
insertion of wait states. The CY7C1351G is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to enable
consecutive Read/Write operations with data being transferred
on every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems that
require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by the four byte write select
(BW_[A:D]) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE₁, CE₂, CE₃) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. In order to avoid bus
contention, the output drivers are synchronously tristated during
the data portion of a write sequence.
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Description
133 MHz
6.5
225
40
100 MHz Unit
8.0
ns
205
mA
40
mA
Errata: For information on silicon errata, see "Errata" on page 18. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05513 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 25, 2013