CY7C1305AV18 Datasheet, PDF (1/20 Pages) Cypress Semiconductor – 18-Mb Burst of 4 Pipelined SRAM with QDR™ Architecture

PRELIMINARY
CY7C1305AV18
CY7C1307AV18
18-Mb Burst of 4 Pipelined SRAM with QDR™ Architecture
Features
Functional Description
• Separate independent Read and Write data ports
— Supports concurrent transactions
• 167 MHz Clock for high bandwidth
— 2.5 ns Clock-to-Valid access time
• 4-Word Burst for reducing the address bus frequency
• Double Data Rate (DDR) interfaces on both Read & Write
Ports (data transferred at 333 MHz) @167 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) accounts for clock skew
and flight time mismatching
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL Inputs and Outputs
• 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball
(11x15 matrix)
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–1.9V)
• JTAG Interface
Configurations
The CY7C1305AV18/CY7C1307AV18 are 1.8V Synchronous
Pipelined SRAMs equipped with QDR™ architecture. QDR
architecture consists of two separate ports to access the
memory array. The Read port has dedicated Data Outputs to
support Read operations and the Write Port has dedicated
Data Inputs to support Write operations. QDR architecture has
separate data inputs and data outputs to completely eliminate
the need to “turn-around” the data bus required with common
I/O devices. Access to each port is accomplished through a
common address bus. Addresses for Read and Write
addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the device’s Read and Write ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 18-bit words (CY7C1305AV18) and four
36-bit words (CY7C1307AV18) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K/K and
C/C) memory bandwidth is maximized while simplifying
system design by eliminating bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
CY7C1305AV18 – 1M x 18
CY7C1307AV18 – 512K x 36
Logic Block Diagram (CY7C1305AV18)
D_[17:0]
18
A_{(17:0) 18}
Address
Register
Write Write Write Write
Reg Reg Reg Reg
Address
Register
18 ^A(17:0)
K
K
CLK
Gen.
Vref
WPS
BWS_[0:1]
Control
Logic
Read Data Reg.
72 ₃₆
36
Control
Logic
RPS
C
C
Reg.
Reg.
Reg.
18
18
Q_[17:0]
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05495 Rev. *A
Revised June 1, 2004