CY62156ESL Datasheet, PDF (1/16 Pages) Cypress Semiconductor – 8-Mbit (512 K x 16) Static RAM

CY62156ESL MoBL^®
8-Mbit (512 K × 16) Static RAM
8-Mbit (512 K × 16) Static RAM
Features
■ High Speed: 45 ns
■ Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
■ Ultra Low Standby Power
❐ Typical standby current: 2 A
❐ Maximum standby current: 8 A
■ Ultra Low Active Power
❐ Typical active current: 1.8 mA at f = 1 MHz
■ Easy Memory Expansion with CE₁, CE₂, and OE Features
■ Automatic Power Down when Deselected
■ CMOS for Optimum Speed and Power
■ Available in Pb-free 48-ball very fine-pitch ball grid array
(VFBGA) packages
Functional Description
The CY62156ESL is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL^®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
in standby mode when deselected (CE₁ HIGH or CE₂ LOW). The
input or output pins (I/O₀ through I/O₁₅) are placed in a high
impedance state when the device is deselected (CE₁ HIGH or
CE₂ LOW), the outputs are disabled (OE HIGH), Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or
a write operation is active (CE₁ LOW, CE₂ HIGH and WE LOW).
To write to the device, take Chip Enable (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇) is
written into the location specified on the address pins (A₀ through
A₁₈). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O₈ through I/O₁₅) is written into the location specified on the
address pins (A₀ through A₁₈).
To read from the device, take Chip Enable (CE₁ LOW and CE₂
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O₀ to I/O₇. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O₈ to I/O₁₅. See the Truth Table on page
11 for a complete description of read and write modes.
Logic Block Diagram
A₁₀
A₉
A₈
A₇
AA₆₅
A₄
A₃
A₂
A₁
A₀
DATA IN DRIVERS
512 K × 16
RAM Array
I/O₀–I/O₇
I/O₈–I/O₁₅
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-54995 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 13, 2013