CY2XL11 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – 100 MHz LVDS Clock Generator

CY2XL11
100 MHz LVDS Clock Generator
Features
■ One LVDS Output Pair
■ Output Frequency: 100 MHz
■ External Crystal Frequency: 25 MHz
■ Low RMS Phase Jitter at 100 MHz, using 25 MHz Crystal
(637 kHz to 10 MHz): 0.53 ps (Typical)
■ Pb-free 8-Pin TSSOP Package
■ Supply Voltage: 3.3V or 2.5V
■ Commercial Temperature Range
Logic Block Diagram
XIN
External
Crystal
CRYSTAL
OSCILLATOR
XOUT
Functional Description
The CY2XL11 is a PLL (Phase Locked Loop) based high
performance clock generator with a crystal oscillator interface
and one LVDS output pair. It is optimized to generate PCI
Express, FC, and other high performance clock frequencies. It
also produces an output frequency that is four times the crystal
frequency. It uses Cypress’s low noise VCO technology to
achieve less than 1 ps typical RMS phase jitter, that meets high
performance systems’ jitter requirements.
LOW-NOISE
PLL
OUTPUT
DIVIDER
CLK
CLK#
Pinouts
OE
Figure 1. Pin Diagram - 8-Pin TSSOP
VDD 1
VSS 2
XOUT 3
XIN 4
8
VDD
7
CLK
6
CLK#
5
OE
Table 1. Pin Definition - 8-Pin TSSOP
Pin Number
1, 8
2
3, 4
Pin Name
VDD
VSS
XOUT, XIN
I/O Type
Power
Power
XTAL output and input
5
OE
CMOS input
6,7
CLK#, CLK
LVDS output
Description
3.3V or 2.5V power supply. All supply current flows through pin 1
Ground
Parallel resonant crystal interface
Output Enable. When HIGH, the output is enabled. When LOW, the
output is high impedance
Differential clock output
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-42886 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 18, 2009
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