CY2CC910_05 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 1:10 Clock Fanout Buffer

COMLINK™ SERIES
CY2CC910
1:10 Clock Fanout Buffer
Features
• Low-voltage operation
• Full-range support:
— 3.3V
— 2.5V
— 1.8V
• Over voltage tolerant input hot swappable
• 1:10 fanout
• Drives either a 50-Ohm or 75-Ohm load
• Low-input capacitance
• Low-output skew
• Low-propagation delay
• Typical (t_pd < 4 ns)
• High-speed operation:
— 200 MHz@1.8V
— 650 MHz@2.5V/3.3V
• Industrial versions available
• Available packages include: SOIC, SSOP
Block Diagram
VDD
4,8
15,20
IN ₁
INPUT
(AVCMOS)
2,6,10
13,17
GND
Description
The Cypress series of network circuits are produced using
advanced 0.35 micron CMOS technology, achieving the indus-
tries fastest logic and buffers.
The Cypress CY2CC910 fanout buffer features one input and
ten outputs. Ideal for conversion from/to 3.3V/2.5V/1.8V
Designed for Data Communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
Cypress employs unique AVCMOS type outputs VOI™
(Variable Output Impedance) that dynamically adjust for
variable impedance matching and eliminate the need for
series damping resistors and reduce noise overall.
3
Q1
5
Q2
7
Q3
9
Q4
11
Q5
12
Q6
14
Q7
16
Q8
18
Q9
19
Q10
OUTPUT
(AVCMOS)
Pin Configuration
IN 1
GND 2
Q1 ³
VDD ⁴
Q2 ⁵
GND ⁶
Q3 ⁷
VDD ⁸
Q4 ⁹
GND ¹⁰
20 VDD
19 Q10
18 Q9
17 _GND
16 Q8
15 _VDD
14 _Q7
13 GND
12 _Q6
11 _Q5
20 pin SOIC/SSOP
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-07348 Rev. *B
Revised October 27, 2005