CY2CC1910 Datasheet, PDF (1/8 Pages) Cypress Semiconductor – 1:10 Clock Fanout Buffer with Output Enable

COMLINK™ SERIES
CY2CC1910
1:10 Clock Fanout Buffer with Output Enable
Features
• Low-voltage operation
• Full-range support:
— 3.3V
— 2.5V
— 1.8V
• 1:10 fanout
• Drives either a 50-Ohm or 75-Ohm load
• Over voltage tolerant input hot swappable
• Low-input capacitance
• Low-output skew
• Low-propagation delay
• Typical (tpd < 4 ns)
• High-speed operation:
— 100 MHz@1.8V
— 200 MHz@2.5V/3.3V
• Industrial versions available
• Available packages include: SOIC, SSOP
Block Diagram
5
OE#
AVCMOS
VDD
6
IN
AVCMOS
3,10
15,22
1,12,13
17,24
Description
The Cypress series of network circuits are produced using
advanced 0.35-micron CMOS technology, achieving the
industries fastest logic and buffers.
The Cypress CY2CC1910 fanout buffer features one input and
ten outputs. Ideal for conversion from/to 3.3V/2.5V/1.8V.
Designed for data communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
Cypress employs unique AVCMOS-type outputs VOI™
(Variable Output Impedance) that dynamically adjust for
variable impedance matching and eliminate the need for
series damping resistors; they also reduce noise overall.
23
Q1
21
Q2
19
Q3
18
Q4
16
Q5
14
Q6
11
Q7
Pin Configuration
GND 1
Q10 2
VDD 3
Q9 4
OE# ₅
IN ₆
GND ₇
GND ₈
Q8 ₉
VDD ₁₀
Q7 ₁₁
GND ₁₂
24 GND
23 Q1
22 VDD
21 ^Q2
20 ^GND
19 ^Q3
18 ^Q4
17 ^GND
16 ^Q5
15 ^VDD
14 ^Q6
13 ^GND
24 pin SOIC/SSOP
GND
9
Q8
4
Q9
2
Q10
OUTPUT (AVCMOS)
Pin Description
Pin Number
Pin Name
Pin Description
1, 7, 8, 12, 13, 17, 20, 24
3,10,15,22
5
G_ND
V_DD
OE#
Ground
Power Supply
Output Enable
Power
Power
LVTTL/LVCMOS
6
IN
Input
LVTTL/LVCMOS
2, 4, 9, 11, 14, 16, 18, 19, 21, 23 Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1 Output
AVCMOS
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07347 Rev. *B
Revised December 26, 2002