CY29947 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – 2.5V or 3.3V, 200-MHz, 1:9 Clock Distribution Buffer

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CY29947
2.5V or 3.3V, 200-MHz, 1:9 Clock Distribution Buffer
Features
• 2.5V or 3.3V operation
• 200-MHz clock support
• LVCMOS-/LVTTL-compatible inputs
• 9 clock outputs: drive up to 18 clock lines
• Synchronous Output Enable
• Output three-state control
• 250 ps max. output-to-output skew
• Pin compatible with MPC947, MPC9447
• Available in Industrial and Commercial temp. range
• 32-pin TQFP package
Description
The CY29947 is a low-voltage 200-MHz clock distribution buff-
er with the capability to select one of two LVCMOS/LVTTL
compatible clock inputs. The two clock sources can be used
to provide for a test clock as well as the primary system clock.
All other control inputs are LVCMOS/LVTTL compatible. The 9
outputs are LVCMOS or LVTTL compatible and can drive 50Ω
series or parallel terminated transmission lines.For series ter-
minated transmission lines, each output can drive one or two
traces giving the device an effective fanout of 1:18. The out-
puts can also be three-stated via the three-state input TS#.
Low output-to-output skews make the CY29947 an ideal clock
distribution buffer for nested clock trees in the most demand-
ing of synchronous systems.
The CY29947 also provides a synchronous output enable in-
put for enabling or disabling the output clocks. Since this input
is internally synchronized to the input clock, potential output
glitching or runt pulse generation is eliminated.
Block Diagram
TCLK0
TCLK1
TCLK_SEL
SYNC_OE
TS#
VDD
0
1
Pin Configuration
VDDC
9 _Q0-Q8
VSS
TCLK_SEL
TCLK0
TCLK1
SYNC_OE
TS#
VDD
VSS
1
24
2
23
3
22
4
5
CY29947
21
20
6
19
7
18
8
17
VSS
Q3
VDDC
Q4
VSS
Q5
VDDC
VSS
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07287 Rev. *C
Revised December 22, 2002