CY28439 Datasheet, PDF (1/22 Pages) SpectraLinear Inc – Clock Generator for Intel Grantsdale Chipset

PRELIMINARY
CY28439
Clock Generator for Intel^ Grantsdale Chipset
Features
• Compliant to Intel^ CK410
• Supports Intel Prescott and Tejas CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100-MHz differential SRC clocks (two selectable
between Fixed and Overclocking)
• 96-MHz differential dot clock
• 48-MHz USB clocks
• 33-MHz PCI clock
• Dial-A-Frequency^
Block Diagram
Xin
Xout
FS_[E:A]
14.318MHz
Crystal
PLL Reference
PLL1
CPU
Divider
VTTPWR_GD#/PD
PLL2
SRC
Divider
PLL3
SATA
Divider
PLL4
Fixed
Divider
SDATA
SCLK
I2C
Logic
Watchdog
Timer
VDD_RE
F
RE
F
IREF
VDD_CPU
CPUT
CPUC
VDD_SRC
SRCT (PCI Ex)
SRCC (PCI Ex)
VDD_SRC
SRCT4_SATA
SRCC4_SATA
VDD_48Mhz
DOT96T
DOT96C
VDD_48
USB48
VDD_48
24/48
VDD_PCI
PCI
VDD_PCI
PCIF
SRESET#
• Watchdog
• Two independent overclocking PLLs
• Low-voltage frequency select input
• I²C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
CPU SRC PCI REF DOT96 USB
x2 x6 x9 x2 x1
x1
24-48M
x1
Pin Configuration
VSS_PCI
1
PCI3
2
*FS_E/PCI4
3
PCI5
4
VSS_PCI
5
VDD_PCI
6
PCIF0
7
**FS_A/PCIF1
8
*FS_B/PCIF2
9
VDD_48 10
**SEL24_48#/24_48M 11
USB48
12
VSS_48
13
DOT96T
14
DOT96C
15
VTTPWRGD#/PD
16
SRCT0
17
SRCC0
18
VDD_SRC
19
VSS_SRC
20
SRCT1
21
SRCC1
22
SRCT2
23
SRCC2
24
VSS_SRC
25
SRCT_SATAT
26
SRCC_SATAC
27
VDD_SRC
28
56
VDD_PCI
55
PCI2
54
PCI1
53 PCI0
52 SRESET#
51 REF1/FS_C**
50 REF0/FS_D**
49 VSS_REF
48 XIN
47 XOUT
46 VDD_REF
45
SCLK
44
SDATA
43 CPUT0
42 CPUC0
41
VDD_CPU
40 CPUT1
39 CPUC1
38
VSS_CPU
37 IREF
36 VSSA
35 VDDA
34 VDD_SRC
33 SRCT4
32
SRCC4
31
SRCT3
30
SRCC3
29 VSS_SRC
* Indicates internal pull-up
** Indicates internal pull-down
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07668 Rev. *D
Revised June 13, 2005