CY24130_08 Datasheet, PDF (1/6 Pages) Cypress Semiconductor – HOTLink II™ SMPTE Receiver Training Clock

CY24130
HOTLink II™ SMPTE Receiver Training
Clock
Features
Benefits
■ Integrated phase-locked loop
■ Low-jitter, high-accuracy outputs
■ 3.3V operation
■ Internal PLL with up to 400-MHz internal operation
■ Meets critical timing requirements in complex system
designs
■ Enables application compatibility
Table 1. Frequency table
Part Number Outputs
CY24130-1
2
CY24130-2
2
Input Frequency
27 MHz (Driven Reference)
27 MHz (Crystal Reference)
Output Frequency Range
1 copy 27-MHz reference clock output
1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)
1 copy 27-MHz reference clock output
1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)
Logic Block Diagram
XIN
XOUT
OSC.
S0
S1
S2
Q
Φ
VCO
P
PLL
OUTPUT
MULTIPLEXER
AND
DIVIDERS
VDDL VDD AVDD AVSS VSS VSSL
CLKA
REFCLK
Table 2. Frequency Select Options
S2
S1
S0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
CLKA
27
36
54
148.50
74.25
OFF, pulled low
OFF, pulled low
OFF, pulled low
REFCLK
27
27
27
27
27
27
27
27
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-07711 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 22, 2008
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