CY23FS08_06 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – Failsafe™ 2.5V/ 3.3V Zero Delay Buffer

CY23FS08
Failsafe™ 2.5V/ 3.3V Zero Delay Buffer
Features
• Internal DCXO for continuous glitch-free operation
• Zero input-output propagation delay
• 100ps typical output cycle-to-cycle jitter
• 110 ps typical Output-output skew
• 1 MHz–200 MHz reference input
• Supports industry standard input crystals
• 200 MHz (commercial), 166 MHz (industrial) outputs
• 5V-tolerant inputs
• Phase-locked loop (PLL) Bypass Mode
• Dual Reference Inputs
• 28-pin SSOP
• Split 2.5V or 3.3V output power supplies
• 3.3V core power supply
• Industrial temperature available
Block Diagram
Functional Description
The CY23FS08 is a FailSafe™ Zero Delay Buffer with two
reference clock inputs and eight phase-aligned outputs. The
device provides an optimum solution for applications where
continuous operation is required in the event of a primary clock
failure.
Continuous, glitch-free operation is achieved by using a
DCXO, which serves as a redundant clock source in the event
of a reference clock failure by maintaining the last frequency
and phase information of the reference clock.
The unique feature of the CY23FS08 is that the DCXO is in
fact the primary clocking source, which is synchronized
(phase-aligned) to the external reference clock. When this
external clock is restored, the DCXO automatically resynchro-
nizes to the external clock.
The frequency of the crystal, which will be connected to the
DCXO must be chosen to be an integer factor of the frequency
of the reference clock. This factor is set by four select lines:
S[4:1]. please see Table 1. The CY23FS08 has three split
power supplies; one for core, another for Bank A outputs and
the third for Bank B outputs. Each output power supply, except
VDDC can be connected to either 2.5V or 3.3V. VDDC is the
power supply pin for internal circuits and must be connected
to 3.3V.
Pin Configuration
REFSEL
XIN XOUT
DCXO
REF1
REF2
FBK
Failsafe^TM
Block
PLL
S[4:1]
Decoder
4
4
CLKA[1:4]
4
CLKB[1:4]
FAIL# /SAFE
REF1 ₁
REF2 ₂
VSSB ₃
CLKB1 ₄
CLKB2 ₅
S2 ₆
S3 ₇
VDDB ₈
VSSB 9
CLKB3 10
CLKB4 11
VDDB 12
VDDC 13
XIN ₁₄
28 REFSEL
27 FBK
26 VSSA
25 CLKA1
24 CLKA2
23 S1
22 S4
21 VDDA
20 VSSA
19 CLKA3
18 CLKA4
17 VDDA
16 FAIL#/SAFE
15 XOUT
28-pin SSOP
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-07518 Rev. *C
Revised January 2, 2006