CY23EP05 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 2.5V or 3.3V,10- 220 MHz, Low Jitter, 5 Output Zero Delay Buffer

CY23EP05
2.5V or 3.3V,10- 220 MHz, Low Jitter, 5 Output
Zero Delay Buffer
Features
Functional Description
• 10 MHz to 220 MHz maximum operating range
• Zero input-output propagation delay, adjustable by
loading on CLKOUT pin
• Multiple low-skew outputs
— 30 ps typical output-output skew
— One input drives five outputs
• 22 ps typical cycle-to-cycle jitter
• 13 ps typical period jitter
• Standard and High drive strength options
• Available in space-saving 150-mil SOIC package
• 3.3V or 2.5V operation
• Industrial temperature available
The CY23EP05 is a 2.5V or 3.3V zero delay buffer designed
to distribute low-jitter high-speed clocks and is available in a
8-pin SOIC package. It accepts one reference input, and
drives out five low-skew clocks. The -1H version operates up
to 220 (200) MHz frequencies at 3.3V (2.5V), and has a higher
drive strength than the -1 devices. All parts have on-chip PLLs
which lock to an input clock on the REF pin. The PLL feedback
is on-chip and is obtained from the CLKOUT pad.
The CY23EP05 PLL enters a power-down mode when there
are no rising edges on the REF input (<~2 MHz). In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 25 µA of current draw.
The CY23EP05 is available in different configurations, as
shown in the Ordering Information table. The CY23EP05-1 is
the base part. The CY23EP05-1H is the high-drive version of
the -1, and its rise and fall times are much faster than the -1.
These parts are not intended for 5V input-tolerant applications
Block Diagram
Pin Configuration
REF
PLL
CLKOUT
CLK1
CLK2
CLK3
CLK4
Top View
REF ¹
8
CLK2 ²
7
CLK1 ³
6
GND ⁴
5
CLKOUT
CLK4
V_DD
CLK3
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-07759 Rev. *B
Revised December 13, 2005