CY14MB064Q1B Datasheet, PDF (1/28 Pages) Cypress Semiconductor – 64-Kbit (8 K × 8) SPI nvSRAM

CY14MB064Q1B/CY14MB064Q2B
PRELIMINARY _{CY14ME064Q1B/CY14ME064Q2B}
64-Kbit (8 K × 8) SPI nvSRAM
64-Kbit (8 K × 8) SPI nvSRAM
Features
■ 64-Kbit nonvolatile static random access memory (nvSRAM)
internally organized as 8 K × 8
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using SPI
instruction (Software STORE)
❐ RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
❐ Support automatic STORE on power-down with a small
capacitor (except for CY14MX064Q1B)
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1million STORE cycles to QuantumTrap
❐ Data retention: 20 years at 85 C
■ High speed serial peripheral interface (SPI)
❐ 40-MHz clock rate SPI write and read with zero cycle delay
❐ Supports SPI mode 0 (0,0) and mode 3 (1,1)
■ SPI access to special functions
❐ Nonvolatile STORE/RECALL
❐ 8-byte serial number
❐ Manufacturer ID and Product ID
❐ Sleep mode
■ Write protection
❐ Hardware protection using Write Protect (WP) pin
❐ Software protection using Write Disable instruction
❐ Software block protection for 1/4, 1/2, or entire array
■ Low power consumption
❐ Average active current of 3 mA at 40 MHz operation
❐ Average standby mode current of 120 A
❐ Sleep mode current of 8 A
Logic Block Diagram
■ Industry standard configurations
❐ Operating voltages:
• CY14MB064Q1B/CY14MB064Q2B: V_CC = 2.7 V to 3.6 V
• CY14ME064Q1B/CY14ME064Q2B: V_CC = 4.5 V to 5.5 V
❐ Industrial temperature
❐ 8-pin small outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
Functional Overview
The Cypress CY14MX064Q combines a 64 Kbit nvSRAM with a
nonvolatile element in each memory cell with serial SPI interface.
The memory is organized as 8 K words of 8 bits each. The
embedded nonvolatile elements incorporate the QuantumTrap
technology, creating the world’s most reliable nonvolatile
memory. The SRAM provides infinite read and write cycles, while
the QuantumTrap cells provide highly reliable nonvolatile
storage of data. Data transfers from SRAM to the nonvolatile
elements (STORE operation) takes place automatically at
power-down (except for CY14MX064Q1B). On power-up, data
is restored to the SRAM from the nonvolatile memory (RECALL
operation). You can also initiate the STORE and RECALL
operations through SPI instruction.
Configuration
Feature
AutoStore
Software STORE
CY14MX064Q1B
No
Yes
CY14MX064Q2B
Yes
Yes
Serial Number
8x8
SI
CS
SCK
WP
SO
Status Register
Manufacturer ID /
Product ID
WRSR/RDSR/WREN
RDSN/WRSN/RDID
SPI Control Logic
Write Protection
Instruction decoder
READ/WRITE
STORE/RECALL/ASENB/ASDISB
Memory
Data & Address
Control
QuantumTrap
8Kx8
SRAM
8Kx8
STORE
RECALL
V_CC
V_CAP
Power Control Block
SLEEP
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-70382 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 3, 2012