CY7C1059DV33_07 Datasheet, PDF (5/9 Pages) Cypress Semiconductor – 8-Mbit (1M x 8) Static RAM

CY7C1059DV33
AC Switching Characteristics
Over the Operating Range^[6]
Parameter
Description
Read Cycle
t_power[7]
V_CC(typical) to the First Access
t_RC
Read Cycle Time
t_AA
Address to Data Valid
t_OHA
Data Hold from Address Change
t_ACE
CE LOW to Data Valid
t_DOE
OE LOW to Data Valid
t_LZOE
t_HZOE
t_LZCE
t_HZCE
OE LOW to Low-Z
OE HIGH to High-Z^{[8, 9]}
CE LOW to Low-Z^[9]
CE HIGH to High-Z^{[8, 9]}
t_PU
CE LOW to Power up
t_PD
CE HIGH to Power down
Write Cycle^{[10, 11]}
t_WC
t_SCE
t_AW
t_HA
t_SA
t_PWE
t_SD
t_HD
t_LZWE
t_HZWE
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low-Z^[9]
WE LOW to High-Z^{[8, 9]}
–10
Min
Max
100
10
10
2.5
10
5
0
5
3
5
0
10
10
7
7
0
0
7
5
0
3
5
–12
Unit
Min
Max
100
μs
12
ns
12
ns
2.5
ns
12
ns
6
ns
0
ns
6
ns
3
ns
6
ns
0
ns
12
ns
12
ns
8
ns
8
ns
0
ns
0
ns
8
ns
6
ns
0
ns
3
ns
6
ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
7. t_POWER is the minimum amount of time that the power supply must be at stable, typical V_CC values until the first memory access can be performed.
8. t_HZOE, t_HZCE, and t_HZWE are specified with a load capacitance of 5 pF as in part (d) of “AC Test Loads and Waveforms” on page 4. Transition is measured when
the outputs enter a high impedance state.
9. At any temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any device.
10. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either
of these signals can terminate the write. The input data setup and hold timing must refer to the leading edge of the signal that terminates the Write.
11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t_HZWE and t_SD.
Document #: 001-00061 Rev. *C
Page 5 of 9
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