DRC3P48D400R2 Datasheet, PDF (8/12 Pages) Crydom Inc., – DRC Series

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TIMING DIAGRAM
Input/Output
1
2
Input A1
TIMING DIAGRAM FOR DRC3R
3
4
5
6
7
8
9
10
Input A3
FWD Direction
100 msec
100 msec
REV Direction
100 msec
interlock
STEP
1, 4, 10
2
3, 9
4
5
DESCRIPTION
Initial Condition. A1 & A3 open
A1 is activated, FWD Output waits for 100msec
FWD direction is activated
A1 changes to off. FWD Output is disabled at the same time
A3 is activated. REV Outputs waits for 100msec
Input A1
Input A3
FWD
REV
Open
Open
Off
Off
Close
Open
On
Off
Open
Close
Off
On
6
REV direction is On
Close
Close
Off
Off
7
Interlock fuction is activated. REV is disabled due to A1 & A3 both being active
8
A3 is open, A1 is closed, activation delayed 100msec
AGENCY APPROVALS
Agency Approvals
Certification in accordance with:
United States Standard for Industrial Control Equipment - UL 508 and
Canadian Standard Association for Industrial Control Equipment – C22.2 No. 14.
China Compulsory Certification for AC Semiconductor Motor Controller-GB14048.6-2008
DRC3 series conforms to the harmonized EN standard EN/IEC 60947-4-2
Electromagnetic Compatibility:
IEC 61000-4-2 : Electrostatic Discharge – Level 3
IEC 61000-4-4 : Electrically Fast Transients – Level 3
IEC 61000-4-5 : Electrical Surges – Level 3
Vibration Resistance:
IEC 60068-2-6 : Amplitude Range 10-55 Hz, Displacement 0.75mm
Shock Resistance:
IEC 60068-2-27 : Peak Acceleration 15g, Duration11msec.
E116949
s _{(Only DRCx40x4x & DRCx48x4x)}
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Copyright © 2017 Crydom Inc. Specifications subject to change without notice.