SCG3040G5 Datasheet, PDF (3/12 Pages) Connor-Winfield Corporation – Synchronous Clock Generator

Table 2
Symbol
V
CC
I_CC
T_OP
F_O
F_REF
F
CAP
F_BW
T_JTOL
T_AQ
J_GEN
Recommended Operating Specifications
Parameter
Minimum
Power Supply Voltage
3.135
Power Supply Current
-
Temperature Range
0
Available Output Frequencies
Q1,Q2
77.76
Reference Frequency
-
Capture/Pull-in Range
-25
Jitter Filter Bandwidth
-
Input Jitter Tolerance
-
(Input Jitter Frequencies > 10 Hz)
Acquisition Time
-
Jitter Generation
Q1,Q2
-
Nominal
3.3
-
-
-
19.44
-
8
-
100
-
Maximum
3.465
270
70
155.52
-
25
15
31.25
-
1
Units
Volts
mA
deg. C
MHz
MHz
ppm
Hz
us
ms
ps RMS
Notes
2, 9
5, 6
3
4
7
Table 3
Symbol
V_IH
V_IL
T_IR
T_IRF
V_OH
V_OL
C
L
T_SKEW
T_RF
DC
Input And Output Characteristics
Parameter
Minimum
Nominal
CMOS Input Characteristics
High Level Input Voltage
2
-
Low Level Input Voltage
0
-
Input Reference Pulse Width
12.5
-
Input Rise and Fall Time (20% to 80%)
-
-
LVPECL Output Characteristics
High Level Output Voltage
2.27
2.34
Low Level Output Voltage
1.49
1.51
Output Capacitance
-
-
Differential Output Skew
-
50
Output Rise and Fall Time (20% to 80%) -
-
Duty Cycle
45
50
Maximum Units
5.5
V
0.8
V
-
nS
5
nS
2.52
V
1.68
V
10
pF
-
ps
1
ns
55
%
Notes
8
5
5
5
5
5
NOTES:
1: Operation of the device at these or any other condition beyond those
listed under Recommended Operating Specifications is not implied.
Exposure to Absolute Maximum Rating conditions for extended
periods of time may affect device reliability.
2: Requires external regulation and supply decoupling. (22uF, 330 pF)
3: 3dB loop response.
4: From a 20 ppm step in reference frequency.
5: With LVPECL termination as defined by figure 8 (Z_O = 50 Ω).
6: Maximum I_CC tested at V_CC = 3.46V
7: Jitter based on SONET OC-48 bandwidth ( 12 kHz - 20 MHz).
8: Avoid meta-stable input signals
9: Vcc ramp rate must be monotonic rising. Ramp must be greater
than 300 V/s from 2V to 3V.
Data Sheet #: SG127 Page 3 of 12 Rev: 00 Date: 04/25/06