SCG3040G5 Datasheet, PDF (1/12 Pages) Connor-Winfield Corporation – Synchronous Clock Generator

2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: [phone]
Fax: [phone]
www.conwin.com
SCG3040G5
Synchronous Clock
Generator
PLL
Bulletin
Page
Revision
Date
Issued By
SG127
1 of 12
00
25 APR 06
ENG
Application
The SCG3040G5 is designed for use as a
reference input for OC-48 Framers and
SERDES. It generates less than 1 psRMS
jitter over the OC-48 bandwidth.
SCG3040G5 is well suited for use in line
cards, service termination cards and similar
functions to provide reliable reference,
phase locked, synchronization for TDM,
PDH, SONET, and SDH network
equipment. The SCG3040G5 provides a
jitter filtered, wander following output signal
synchronized to a superior Stratum or peer
input reference signal.
This product is ROHS-5 compliant.
ROHS-5 indicates that this product is
ROHS compliant except for lead from those
manufacturers wishing to take the lead
exemption.
Features
• 3.3V High Precision
PLL
• Two Differential
LVPECL Outputs.
155.52 MHz or 77.76
MHz
• 19.44 MHz CMOS
Input Reference
• Reference Duty Cycle
Tolerant
• Low Temperature
Reflow Surface
Mounting
• ROHS-5 compliant