CN7221 Datasheet, PDF (6/18 Pages) Conexant Systems, Inc – Home Networking Physical Layer Device with Integrated Analog Front End Circuitry

LANfinity™ CN7221
RxPKT  Carrier Sense Asserted
HLAN_TX_CLK
HLAN_TX_EN
HLAN_TXD
Home Networking PHY with Integrated AFE
HLAN_RX_CLK
HLAN_CRS
HLAN_RXD
HLAN_COL
HLAN_RX_CLK becomes disabled (and left in the high state) as soon as HLAN_CRS is asserted. HLAN_CRS may be asserted at
a multiple of 116.7ns after the rising edge of HLAN_RX_CLK (that is, 0ns, 116.7ns, 233.3ns, 350.0ns, or 466.7ns). The clock is
re-enabled about 135 uS into the packet.
RxPKT  HLAN_RX_CLK Active and HLAN_CRS Cleared
HLAN_TX_CLK
HLAN_TX_EN
HLAN_TXD
HLAN_RX_CLK
HLAN_CRS
HLAN_RXD
HLAN_COL
HLAN_RX_CLK and HLAN_TX_CLK are unrelated to each other during this time. When a symbol has been received and
decoded, HLAN_RX_CLK toggles at a rate of 233.3ns (full period, 50% duty cycle) in order to shift out the three to six bits
encoded in the symbol. The middle portion of this diagram shows the end of the preamble, followed by an SFD and the
beginning of the datagram. HLAN_CRS will fall approximately 16us after the last received symbol. Once HLAN_CRS falls,
HLAN_RX_CLK and HLAN_TX_CLK are toggled continuously at 233.3ns for 97 cycles, after which the PHY returns to the Idle
state.
TxPKT  HLAN_TX_EN Asserted
HLAN_TX_CLK
HLAN_TX_EN
HLAN_TXD
HLAN_RX_CLK
HLAN_CRS
HLAN_RXD
HLAN_COL
Once HLAN_TX_EN is asserted, the PHY stops HLAN_RX_CLK, asserts HLAN_CRS, and toggles HLAN_TX_CLK at 233.3ns.
6
Conexant
LAN-056, Rev. A
PROPRIETARY INFORMATION