RS8953B Datasheet, PDF (42/173 Pages) Conexant Systems, Inc – High-Bit-Rate Digital Subscriber Line (HDSL) channel unit

3.0 Circuit Descriptions
3.2 PCM Channel
RS8953B/8953SPB
HDSL Channel Unit
3.2.2 PCM Receive
The PCM receive formatter shown in Figure 3-9 constructs the serial data (RSER)
output according to receive combination table settings and the frame format
defined by the PCM Formatter Registers (see Table 4-4). The PCM receiver
operates on the clock edge selected by RCLK_SEL [CMD_2; addr 0xE6] and
references the PCM receive timebase and RSER frame location to the alignment
provided by the master HDSL channel’s receive 6 ms frame. Therefore, the
position of bit 0, frame 0 output on RSER, is slaved to the HDSL receiver
selected as master by MASTER_SEL [CMD_5; addr 0xE9]. The RSER timing
relationship with respect to PCM 6 ms sync is shown in Figure 3-10. PCM 6 ms
sync is created from the HDSL 6 ms frame delayed by the programmed
RFIFO_WL [addr 0xCD] value, as shown in Figure 3-13.
Figure 3-9. PCM Receive Block Diagram
BER_SEL
BER Meter
TSER
RSER
PP_LOOP
DBANK 1
DBANK 2
DBANK 3
SIG Table
RFIFO 1
RFIFO 2
RFIFO 3
FROM CH1 RMAP
FROM CH2 RMAP
FROM CH3 RMAP
DROP
RMSYNC
RCLK
TMSYNC
Combine Table
PCM Receive Timebase
Frame
Bit
MF Frame MF
Delay Delay Length Length Count
= Command Register Bit
RX_RST
MASTER_SEL
RFIFO_WL
RCLK_INV
RCLK_SEL
CH1 RSYNC
CH2 RSYNC
CH3 RSYNC
DPLL RCLK
EXCLK
TCLK
3-10
Conexant
N8953BDSB