RS8953B Datasheet, PDF (161/173 Pages) Conexant Systems, Inc – High-Bit-Rate Digital Subscriber Line (HDSL) channel unit

RS8953B/8953SPB
HDSL Channel Unit
6.0 Electrical and Timing Specifications
6.1 Absolute Maximum Ratings
6.1.5 MPU Interface Timing
Motorola- (MPUSEL = 1) and Intel- (MPUSEL = 0) style microprocessor bus
timing, as follows:
Table 6-9. MPU Interface Timing Requirements
Symbol
Parameter
1
ALE Pulse-Width High
2
Address Input Setup to ALE Falling
3
Address Input Hold after ALE Low
5
Data Input Setup to End of Write Pulse
6
Data Input Hold After Write Pulse
7
WR* Setup to Start of Read or Write Pulse
8
WR* Hold after Read or Write Pulse
9
ALE Hold after Read or Write Pulse
10
Write Pulse-Width:
WR*, RD*, and CS* Low (MPUSEL = 1)
RD* = 1, WR*, and CS* Low (MPUSEL = 0)
11
Read Pulse Width (WR* = 1, RD* and CS* Low)
Read Pulse Width (WR* = 1, RD* and CS* Low)
Address = 0x3C only.
Minimum
20
10
7
10
8
10
10
8
2 × ------1--------
f_GCLK
26
2
×
------1--------
f_GCLK
Maximum
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 6-10. MPU Interface Switching Characteristics
Symbol
Parameter
12
Data Out Enable (Low Z) after Start of Read Pulse
13
Data Out Valid After Start of Read Pulse (Access Time)
14
Data Out Hold After End of Read Pulse
15
Data Out Disable (High Z) after End of Read Pulse
16
INTR* Hold After End of Write Pulse
(when writing interrupt mask or clear registers)
17
INTR* Delay from End of Write Pulse
(when writing interrupt mask or enable registers)
Minimum
2
1
5
Maximum
26
25
20
Units
ns
ns
ns
ns
ns
ns
N8953BDSB
Conexant
6-7