CY14B101Q1_10 Datasheet, PDF (12/24 Pages) Cypress Semiconductor – 1 Mbit (128K x 8) Serial SPI nvSRAM

CY14B101Q1
CY14B101Q2
CY14B101Q3
CS
SCK
SI
Figure 12. Burst Mode Read Instruction Timing
01 2 3 456 7 01 2 3 45 6 7
20 21 22 23 0 1 2 3 4 5 6 7 0 7 0 1 2 3 4 5 6 7
Op-Code
17-bit Address
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 A16
MSB
A3 A2 A1 A0
LSB
Data Byte 1
Data Byte N
SO
D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
MSB
LSB
CS
SCK
SI
SO
Figure 13. Write Instruction Timing
0 1 2 34 5 67 0 1 23 4 56 7
20 21 22 23 0 1 2 3 4 5 6 7
00
Op-Code
0000100 00
MSB
00
17-bit Address
0 0 A16
HI-Z
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
LSB MSB
Data
LSB
Figure 14. Burst Mode Write Instruction Timing
CS
SCK
SI
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 20 21 22 23 0 1 2 3 4 5 6 7 0 7 0 1 2 3 4 5 6 7
Data Byte 1
Data Byte N
Op-Code
17-bit Address
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 A16 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB MSB
LSB
SO
HI-Z
nvSRAM Special Instructions
CY14B101Q1/CY14B101Q2/CY14B101Q3 provides four
special instructions which enables access to four nvSRAM
specific functions: STORE, RECALL, ASDISB, and ASENB.
Table 8 lists these instructions.
Software STORE
When a STORE instruction is executed, nvSRAM performs a
Software STORE operation. The STORE operation is issued
irrespective of whether a write has taken place since last STORE
or RECALL operation.
Table 8. nvSRAM Special Instructions
Function Name
STORE
RECALL
ASENB
ASDISB
Opcode
0011 1100
0110 0000
0101 1001
0001 1001
Operation
Software STORE
Software RECALL
AutoStore Enable
AutoStore Disable
To issue this instruction, the device must be write enabled (WEN
bit = ‘1’). The instruction is performed by transmitting the STORE
opcode on the SI pin following the falling edge of CS. The WEN
bit is cleared on the positive edge of CS following the STORE
instruction.
Document #: 001-50091 Rev. *D
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