CSRV065V0P_12 Datasheet, PDF (3/5 Pages) Comchip Technology – Low Capacitance ESD Protection Array

Low Capacitance ESD Protection Array
RATING AND CHARACTERISTIC CURVES (CSRV065V0P)
Fig. 1 - Power derating curve
110
100
90
80
70
60
50
40
30
20
10
0
0
25
50
75
100 125 150
Ambient temperature (°C)
Fig. 2 - Clamping voltage vs.
Peak pulse current
12
11
10
9
8
7
6
5
4
3
I/O pin to GND PIN
Waveform
Parameters:
tr=8us
td=20us
2
1
0
4.5 5.0
5.5
6.0
6.5
7.0 7.5
Peak pulse current (A)
Fig.3 - Forward voltage v.s.
forward current
4.0
3.5
3.0
2.5
2.0
1.5
1.0
I/O pin to GND PIN
Waveform
Parameters:
tr=8us
td=20us
0.5
0
4.5 5.0
5.5
6.0
6.5
7.0 7.5
Peak pulse current(A)
Fig.4 - Typical variation of CIN v.s. VIN
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
VDD =5V,GND =0V,f =1MHz,TA=25°C
0.2
0.0
0
1
2
3
4
5
Input voltage (V)
Fig. 5 - Typical variation of CIN v.s.
temperature
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
VDD =5V,GND =0V,VIN =2.5V f=1MHz
1.05
1.00
20
40
60
80
100 120
Temperature (°C)
Fig. 6 - Transmission line pulsing
(TLP) measurement
18
16
14
V_pulse
12
Pulse from a
transmission line
TLP_I
10
100ns
+
TLP_V DUT
8
6
4
I/O to GND
2
0
0 1 2 3 4 5 6 78
Transmission line pulsing(TLP)voltage(V)
Fig.7 -Transmission line pulsing
(TLP) measurement
18
16
14
V_pulse
12
Pulse from a
transmission line
TLP_I
10
100ns
+
TLP_V DUT
8
-
6
4
VDD to GND
2
0
0 1 2 3 4 5 6 7 8 9 10
Transmission line pulsing(TLP)voltage(V)
QW-BP010
Comchip Technology CO., LTD.
REV:C
Page 3