FX949 Datasheet, PDF(13/25 Page) CML Microcircuits

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FX949 Datasheet, PDF (13/25 Pages) CML Microcircuits – CDPD Wireless Modem Data Pump

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CDPD Wireless Modem Data Pump

FX949

Write Only Register Description

TXDATA0 to TXDATA46 Registers (Hex address $00 to $2E)

These 47 registers can be loaded with 6-bit symbols when the TXF bit in the IRQ FLAGS register is "1". On

loading the 47th symbol, the device will generate the 16 symbol parity code and begin the transmit sequence.

These registers are buffered, therefore after the TXF bit has gone to "1" there are 47 x 6 bit periods minus the

time to generate the 16 parity symbols in which to load all registers, i.e. approximately 14 msec. The

controlling ÂµP has to re-load the buffer with new data within this time otherwise the old data will be sent again.

TIMER Register (Hex address $2F)

This register sets a timer to expire from 1 to 255 seconds ("0" disables and powersaves it). The time starts

from when the register is first set and expires when the programmed time has passed. On expiry, the TIMEF

bit is set in the IRQ FLAGS register and an interrupt may occur. The timer is 1-shot and does not restart until it

is programmed again. After power up the TIMEF bit should be reset to "0" in order to initialise the timer.

CONTROL Register (Hex address $30)

This register is used to control the functions of the device as described below:

ACQ

(Bit 7)

This bit controls the way in which the receiver locks onto the phase and amplitude of

the incoming signal. When a carrier has been detected, this bit should be set high

for at least 16 signal-bit periods, during which time the receiver measures the signal

level (Fast Peak Detect) and sets its phase locked loop (PLL) bandwidth wide

enough to lock to the received signal in less than 8 zero crossings. When the ACQ

bit is returned low, level measurement enters the slower but more accurate

Averaging Peak Detect mode; the PLL enters its medium bandwidth for about 30

signal-bit periods, after which time it will continue in its narrow bandwidth mode.

RXHOLD

(Bit 6)

When this bit is set to "1" the receiver "bit synchronisation" PLL will lock. It can be

used during times when the signal fades, so that when the signal returns the

receiver is still very close to good "bit synchronisation". When this bit is set to "0",

the device uses its normal PLL acquisition sequence for "bit synchronisation". When

ACQ is high, the RXHOLD bit has no effect.

PSRX

(Bit 5)

When this bit is "1" the receiver is powersaved. When this bit is "0" the receiver is

enabled. After power up, this bit should be programmed to "1" in order to initialise

the receiver.

PSTX

(Bit 4)

When this bit is "1" the transmitter is powersaved. When this bit is "0" the transmitter

is enabled. Transmission starts as soon as the PSTX bit goes to "0". Before that

time, the CI bit and the TXDATA symbols should be set up for the first transmission.

Transmission is terminated as soon as the PSTX bit goes to "1". After power up, this

bit should be programmed to "1" in order to initialise the transmitter.

(Bit 3)

This bit sets the continuity indicator for transmission. It should be set to "1" when

there are more blocks to follow and set to "0" when the last block begins. The first

47 symbol block transmitted after this bit has gone from "0" to "1" is preceded by the

"dotting sequence" and the reverse synchronisation.

D/949/5

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