M-8888 Datasheet, PDF (7/14 Pages) Clare, Inc. – DTMF Transceiver

Common Crystal Connection
Equations
Application Circuit (Single-Ended Input)
M-8888
Internal Register Functions
RS0 RD
0
1
0
0
1
1
1
0
WR Function
0
Write to transmitter
1
Read from receiver
0
Write to control register
1
Read from status register
CRA Bit Positions
b3
b2
RSEL
IRQ
b1
CP/DTMF
b0
TOUT
CRB Bit Positions
b3
b2
C/R
S/D
b1
TEST
b0
BURST
Staus Register Description
Bit
b0 IRQ
Name
b1 Transmit data register empty
(burst mode only)
b2 Receive data register full.
b3 Delayed Steering
Status Flag Set
Interrupt has occurred. Bit one (b1)
and/or bit 2 (b2) is set.status register is read.
Pause duration has terminated and transmitter
is ready for new data.
Valid data is in the receive data register.
Set on valid detection of the absence of a
DTMF signal.
Rev. 1
www.clare.com
Status Flag Cleared
Interrupt is inactive. Cleared after
Cleared after status register is read or
when not in burst mode.
Cleared after status register is read.
Cleared on detection of a valid DTMF
signal.
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