M-8888 Datasheet, PDF (3/14 Pages) Clare, Inc. – DTMF Transceiver

M-8888
switched capacitor bandpass filters with bandwidths
that correspond to the low and high group frequencies
listed in the Tone Encoding/Decoding below. The low
group filter incorporates notches at 350 and 440 Hz,
providing excellent dial tone rejection. Each filter out-
put is followed by a single-order switched capacitor fil-
ter that smoothes the signals prior to limiting. Limiting
is performed by high-gain comparators with hysteresis
to prevent detection of unwanted low-level signals.
The comparator outputs provide full-rail logic swings
at the incoming DTMF signal frequencies.
A decoder employs digital counting techniques to
determine the frequencies of the incoming tones, and
to verify that they correspond to standard DTMF fre-
quencies. A complex averaging algorithm protects
against tone simulation by extraneous signals (such
as voice), while tolerating small deviations in frequen-
cy. The algorithm provides an optimum combination of
immunity to talkoff with tolerance to interfering fre-
quencies (third tones) and noise. When the detector
recognizes the presence of two valid tones (referred to
as signal condition), the early steering (ESt) output
goes to an active state. Any subsequent loss of signal
condition will cause ESt to assume an inactive state.
Tone Encoding/Decoding
F_LOW F_HIGH Digit D3
D2 D1
D0
697 1209 1
0
0
0
1
697 1336 2
0
0
1
0
697 1477 3
0
0
1
1
770 1209 4
0
1
0
0
770 1336 5
0
1
0
1
770 1477 6
0
1
1
0
852 1209 7
0
1
1
1
852 1336 8
1
0
0
0
852 1477 9
1
0
0
1
941 1336 0
1
0
1
0
941 1209 *
1
0
1
1
941 1477 #
1
1
0
0
697 1633 A
1
1
0
1
770 1633 B
1
1
1
0
852 1633 C
1
1
1
1
941 1633 D
0
0
0
0
0 = logic low, 1 = logic high
Basic Steering Circuit
by an external RC time constant driven by ESt. A logic
high on ESt causes V_C (see the Basic Steering Circuit
above) to rise as the capacitor discharges. Provided
that the signal condition is maintained (ESt remains
high) for the validation period (t_GTP), V_C reaches the
threshold (V_TSt) of the steering logic to register the
tone pair, latching its corresponding 4-bit code (see
the Tone Encoding/Decoding on left) into the receive
data register.
At this point the StGT output is activated and drives V_C
to V_DD. StGT continues to drive high as long as ESt
remains high. Finally, after a short delay to allow the
output latch to settle, the delayed steering output flag
goes high, signaling that a received tone pair has
been registered. It is possible to monitor the status of
the delayed steering flag by checking the appropriate
bit in the status register. If interrupt mode has been
selected, the IRQ/CP pin will pull low when the
delayed steering flag is active.
The contents of the output latch are updated on an
active delayed steering transition. This data is pre-
sented to the 4-bit bidirectional data bus when the
receive data register is read. The steering circuit works
in reverse to validate the interdigit pause between sig-
nals. Thus, as well as rejecting signals too short to be
considered valid, the receiver will tolerate signal inter-
ruptions (dropout) too short to be considered a valid
pause. This capability, together with the ability to
select the steering time constants externally, allows
the designer to tailor performance to meet a wide vari-
ety of system requirements.
Steering Circuit:
Before a decoded tone pair is registered, the receiver
checks for a valid signal duration (referred to as “char-
acter recognition condition”). This check is performed
Guard Time Adjustment: The simple steering circuit
shown in the Basic Steering Circuit above is adequate
for most applications. Component values are chosen
according to the formula:
t_REC = t_DP + t_GTP
T_ID = t_DA + t_GTA
Rev. 1
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