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CPC7583_1 Datasheet, PDF (15/21 Pages) Clare, Inc. – Line Card Access Switch
CPC7583
20 Hz ringing hold this input state for 25 ms. During
this hold period, toggle the inputs from the ringing
state to the talk state. After the 25 ms, release TSD to
return switch control to the input pins INTESTout,
INRINGING, INTESTin and the latch control pin.
2.2.1 Make-Before-Break Operation (Ringing to Talk Transition)
State INRINGING INTESTIN INTESTOUT Latch
Ringing 1
0
0
Make-
before- 0
0
0
break
0
Talk
0
0
0
Break Ring Ring All Other
TSD
Timing
Switches Return Access Test
1 and 2 Switch 3 Switch 4 Switches
Floating
-
Off
On
On
Off
SW4 waiting for next
zero-current crossing to turn
off. Maximum time is one-half
of ringing. In this transition
Floating state, current that is limited to On
Off
On
Off
the dc break switch current
limit value will be sourced
from the ring node of the
SLIC.
Floating
Zero-cross current has
occurred
On
Off
Off
Off
2.2.2 Break-Before-Make Operation (Ringing to Talk Transition)
State INRINGING INTESTIN INTESTOUT Latch
Ringing 1
0
0
All off
1
0
1
0
All off
1
0
1
Talk
0
0
0
Break Ring Ring All Other
TSD
Timing
Switches Return Access Test
1 and 2 Switch 3 Switch 4 Switches
Floating
-
Off
On
On
Off
Hold this state for one-half of
Floating ringing cycle. SW4 waiting for Off
Off
On
Off
zero current to turn off.
Floating
Zero current has occurred.
SW4 has opened
Off
Off
Off
Off
Floating Close break switches
On
Off
Off
Off
2.3 Alternate Break-Before-Make Operation
Note that break-before-make operation can also be
achieved using TSD as an input. In lines 2 and 3 of the
table “Break-Before-Make Operation (Ringing to Talk
Transition)” on page 15, instead of using the logic input
pins to force the all-off state, force TSD to ground. This
overrides the logic inputs and also forces the all off
state. Hold this state for one-half of the ringing cycle.
During this TSD forced all-off state, change the inputs
from the power ringing state (INRING = 1, INTESTIN = 0,
INTESTOUT = 0) to the talk state (INRING = 0,
INTESTIN = 0, INTESTOUT = 0). After the hold period,
release TSD to return switch control to the input pins
which will set the talk state.
2.4 Data Latch
The CPC7583 has an integrated data latch. The latch
operation is controlled by logic-level input at the
LATCH pin. The data input of the latch are the input
pins, while the output of the data latch is an internal
node used for state control. When the LATCH control
pin is at logic 0, the data latch is transparent and data
control signals flow directly through to state control. A
change in input will be reflected by a change in switch
state. When the LATCH control pin is at logic 1, the
data latch is active and a change in input control will
not affect switch state. The switches will remain in the
position they were in when the LATCH changed from
R06
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