CPC75282 Datasheet, PDF (14/19 Pages) Clare, Inc. – Line Card Access Switch

CPC75282
Break-before-make operation occurs when the ringing
switches open before the break switches, SW1 and
SW2, close.
State
Ringing
All-Off
All-Off
Talk
CFG=0, P3=0
P2 P1
1
0
1
1
1
1
0
0
2.3.5: Break-Before-Make Ringing to Talk Transition Logic Sequence CPC7592xA/B
LATCH_x
0
OFF_x
1
0
0
1
Timing
Break
Switches
1_x & 2_x
-
Off
Hold this state for at least one-half of the
ringing cycle. SW4 waiting for zero
Off
current to turn off.
Zero current has occurred.
SW4 has opened
Off
Break switches close.
On
Ringing
Return
Switch
3_x
On
Off
Off
Off
Ringing Test
Switch Switches
4_x
5_x & 6_x
On
Off
On
Off
Off
Off
Off
Off
2.3.6 Break -Before- Make Operation
Break-before-make operation can be achieved using
OFF_x to disable all of the switches when pulled to a
logic low. Although logically disabled, an active
(closed) ringing switch, SW4, will remain closed until
the next zero crossing current event.
1. Pull OFF_x to a logic low to end the ringing state.
This opens the ringing return switch, SW3, and
prevents any other switches from closing.
2. Keep OFF_x low for at least one-half the duration
of the ringing cycle period to allow sufficient time
for a zero crossing current event to occur and for
the circuit to enter the break-before-make state.
3. During the OFF_x low period, set the P1, P2, and
P3 inputs to the idle/talk state.
4. Release OFF_x , allowing the internal pull-up to
activate the break switches.
2.4 Data Latch
The CPC75282 has integrated transparent data
latches. The latch enable operation is controlled by
logic input levels at the LATCH_x pin. Data input to the
latch is via the input pins P1, P2, and P3 while the
outputs of the data latch are internal nodes used for
state control. When the latch enable control pin is at a
logic 0 the data latch is transparent and the input
control signals flow directly through the data latch to
the state control circuitry. A change in input will be
reflected by a change in the switch states.
Whenever the latch enable control pin is at logic 1, the
data latch is active and data is locked. Subsequent
changes to the input controls P1, P2, and P3 will not
result in a change to the control logic or affect the
existing switch states.
The switches will remain in the state they were in
when the LATCH_x changes from logic 0 to logic 1, and
will not respond to changes in input as long as the
LATCH_x is at logic 1. However, neither the T_SDx nor
the OFF_x are affected by the latch function. Since
internal thermal shutdown control and external OFF_x
control is not affected by the state of the latch enable
input, T_SDx and OFF_x will override state control.
2.5 T_SD Pin Description
The T_SDx pins are bidirectional I/O structures with
internal pull-up resistors sourced from V_DD. As
outputs, these pins indicate the status of the thermal
shutdown circuitry for the associated channels.
Typically, during normal operation, these pins will be
pulled up to V_DD , but, under fault conditions that
create excess thermal loading, the channels will enter
thermal shutdown and a logic low will be output.
As inputs, the T_SDx pins are utilized to place the
channel into the All-Off state by simply pulling the
input low. For applications using low-voltage logic
devices (lower than V_DD), Clare recommends the use
of an open-collector or an open-drain type output to
control T_SDx. This avoids sinking the T_SDx pull up bias
current to ground during normal operation when the
All-Off state is not required. If T_SDx is set to a logic 1 or
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