CPC5601 Datasheet, PDF (12/14 Pages) Clare, Inc. – Auxiliary Programmable Driver IC

CPC5601
3. Programming
3.1 Latch Circuit Description
Data applied to the input pin is optically coupled to the
shift register through a pulse generator. Each low-to-
high transition in the pulse generator triggers a clock
pulse. Clock pulses are applied to the CLK input of six
3.2 Programming Protocol
rising-edge-triggered flip-flops. The non-inverted input
data is fed to the flip-flops at all times, but the flip-flops
are only clocked on receipt of a pulse from the pulse
generator. The flip-flops drive six FET switches.
Figure 6. Latch Circuit Timing to Turn an Output On
INPUT (pin 3)
t0
>=50µs (tsetup)
200µs
140µs
CLOCK
Transition after setup time
initiates clock pulse
thold
B1 (pin 13)
B1 output FET off (drain open)
First flip-flop reads data
at the rising edge of the clock
B1 output FET on (sinking current)
A setup pulse on the input of at least 50 µS starts the
bit programming sequence. The trailing edge of the
setup pulse starts a timer on the CPC5601 (t0). After
140 µS, the value of the input is latched into the shift
register.
To set an output, hold the input high for 200 µS from
the leading edge after the setup pulse. This turns on
the corresponding open-drain FET to sink current.
Figure 7. Latch Circuit Timing to Turn an Output Off
t0
>=50m s (tsetup)
50m s
140m s
INPUT (pin 3)
150m s min
CLOCK
Transition after setup time
initiates clock pulse
B1 (pin 13)
B1 output FET on (sinking current)
First flip-flop reads data
at the rising edge of the clock
B1 output FET off (drain open)
To clear an output, hold the input high for 50 µS after
the setup pulse, then take the input low for at least 150
µS.
Repeat the sequence of the setup pulse followed by
the appropriate input condition for each successive bit.
Bear the following in mind while programming the
CPC5601:
12
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