CMI8788_17 Datasheet, PDF (11/25 Pages) C&K Components – High Performance PCI Audio Processor

Oxygen^TMHD CMI8788
High Performance PCI Audio Processor
XAC97_SDO0
XAC97_SDO1
XAC97_RST0
XAC97_RST1
XAC97_MCLK
XSPI_DIN/
XMSDA
XSPI_CLK/
XMSCL
XSPI_DOUT/
XA1
XSPI_CEN0/
XA0
XSPI_CEN1/
XCID0
XSPI_CEN2/
XCID1
XSPI_CEN3/
XCID2
64
DO AC97 serial data output 0.
59
DO AC97 serial data output 1.
60
DO AC97 codec reset 0.
57
DO AC97 codec reset 1.
65
DO AC97 master clock 24.5760M for AC97 codec.
Serial Port Interface
73
DIO, PU SPI data input. This pin is shared with 2-wire master serial data.
74
DIO, PU SPI clock output. This pin is shared with 2-wire master serial clock.
SPI data output. This pin is shared with 2-wire Codec address A1.
75
DIO, PU It is also used as XAC97_SDI1 and XADC1_SDIN1 configuration at
the rising edge of XRST (input, 1: XAC97_SDI1, 0: XADC1_SDIN1).
SPI chip enable, which select the codec #0 to be controlled. It is
shared with I2C Codec address A0. It is also used as XGPIO3~4 and
77
DIO, PU _{SSCL/SSDA configuration (input, 1: GPIO3~4, 0: SSCL/SSDA) at the}
rising edge of XRST.
SPI chip enable, which select the codec #1 to be controlled
78
DIO, PU (output). It is shared with codec ID 0 configuration (input) at the
rising edge of XRST.
SPI chip enable, which select the codec #2 to be controlled
79
DIO, PU (output). It is shared with codec ID 1 configuration (input) at the
rising edge of XRST.
SPI chip enable, which select the codec #3 to be controlled
80
DIO, PU (output). It is shared with codec ID 2 configuration (input) at the
rising edge of XRST.
XSPI_CEN4/
XEESK
68
DO ^{SPI chip enable, which select the codec #4 to be controlled. It is shared}
with EEPROM serial clock.
XSPI_CEN5/
XEEDO
69
DO ^{SPI chip enable, which select the codec #5 to be controlled. It is shared}
with EEPROM serial data out.
2-Wire Master Serial Bus
XMSDA/ XSPI_DIN
73
DIO, PU 2-wire serial bus data. This pin is shared with SPI data input.
XMSCL/ XSPI_CLK
74
DIO, PU 2-wire serial bus clock. This pin is shared with SPI clock output.
XA1/
XSPI_DOUT
2-wire serial bus codec address A1. This pin is shared with SPI data
output. It is also used as XAC97_SDI1 and XADC1_SDIN1
75
DIO, PU _{configuration at the rising edge of XRST (input, 1: XAC97_SDI1, 0:}
XADC1_SDIN1).
XA0/
XSPI_CEN0
2-wire serial bus codec address A0. This pin is shared with SPI chip
77
DIO, PU ^{enable, which select the codec #0 to be controlled. It is also used}
as XGPIO3~4 and SSCL/SSDA configuration (input, 1: GPIO3~4, 0:
SSCL/SSDA) at the rising edge of XRST.
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