CMI8788_17 Datasheet, PDF (10/25 Pages) C&K Components – High Performance PCI Audio Processor

Oxygen^TMHD CMI8788
High Performance PCI Audio Processor
XTXD
XRXD
XDAC_MCLK
XDAC_LRCK
XDAC_BCLK
XDAC_SDOUT0
XDAC_SDOUT1
XDAC_SDOUT2
XDAC_SDOUT3
XADC1_MCLK
XADC1_LRCK
XADC1_BCLK
XADC1_SDIN
XAC97_SDI1/
XADC1_SDIN1
XADC2_MCLK
XADC2_LRCK
XADC2_BCLK
XADC2_SDIN
XGPIO5/
XADC3_MCLK
XGPIO6/
XADC3_BCLK
XGPIO7/
XADC3_LRCK
XGPIO8/
XADC3_SDIN
XAC97_BCLK
XAC97_SDI0
XAC97_SDI1/
XADC1_SDIN1
XAC97_SYNC
MPU-401 MIDI UART Interface
MP-401 MIDI transmitter (output). It is also used as XGPIO5~8 and
54
DIO, PU I2S ADC 3 configuration (input, 0: GPIO5~8, 1: I2S ADC 3) at the
rising edge of XRST.
55
DI, PU MPU401 MIDI receiver.
I2S Interface
82
DO I2S DAC master clock output.
83
DIO I2S DAC Left/Right sample clock.
84
DIO I2S DAC bit clock.
85
DO I2S DAC channel 0,channel 1 serial data output.
86
DO I2S DAC channel 2,channel 3 serial data output.
87
DO I2S DAC channel 4,channel 5 serial data output.
88
DO I2S DAC channel 6,channel 7 serial data output.
90
DO I2S ADC 1 and I2S ADC 4 master clock output.
91
DIO I2S ADC 1 Left/Right sample clock.
92
DIO I2S ADC 1 bit clock.
93
DI, PU I2S ADC 1 serial data input.
I2S ADC 1 serial data input 1. This pin is shared with AC97 serial
58
DI, PD ^{data input 1, and determined by XSPI_DOUT/XA1 input}
configuration at the rising edge of XRST.
94
DO I2S ADC 2 master clock output.
95
DIO I2S ADC 2 Left/Right sample clock.
96
DIO I2S ADC 2 bit clock.
97
DI, PU I2S ADC 2 serial data input.
I2S ADC 3 master clock output. This pin is shared with XGPIO5,
98
DIO, PD ^{which is determined by XTXD input configuration at the rising edge}
of XRST.
99
DIO, PD
I2S ADC 3 bit clock. This pin is shared with XGPIO6, which is
determined by XTXD input configuration at the rising edge of XRST.
I2S ADC 2 Left/Right sample clock. This pin is shared with XGPIO7,
100
DIO, PD which is determined by XTXD input configuration at the rising edge
of XRST.
101
DIO, PD
GPIO8, default input. This pin is shared with XADC3_SDIN, which
determined by XTXD input configuration at the rising edge of XRST.
AC-Link Interface
63
DI, PU AC97 serial clock input8
62
DI, PD AC97 serial data input 0
58
DI, PD ^{AC97 serial data input 1. This pin is shared with XADC1_SDIN1, and}
determined by XSPI_DOUT/XA1 input configuration at the rising
edge of XRST.
61
DO AC97 frame synchronization.
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